diff options
| author | Tony Luck <tony.luck@intel.com> | 2022-01-21 09:47:38 -0800 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2022-01-25 18:40:30 +0100 |
| commit | e464121f2d40eabc7d11823fb26db807ce945df4 (patch) | |
| tree | dccb485c4016c29e2ad77e76f2c922167e90b14c /arch/arm/kernel | |
| parent | 1f52b0aba6fd37653416375cb8a1ca673acf8d5f (diff) | |
x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN
Missed adding the Icelake-D CPU to the list. It uses the same MSRs
to control and read the inventory number as all the other models.
Fixes: dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN")
Reported-by: Ailin Xu <ailin.xu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220121174743.1875294-2-tony.luck@intel.com
Diffstat (limited to 'arch/arm/kernel')
0 files changed, 0 insertions, 0 deletions