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authorChintan Vankar <[email protected]>2024-04-22 18:15:15 +0530
committerJakub Kicinski <[email protected]>2024-04-24 19:56:37 -0700
commit5bd8ebe4693c21851ef8a05343d43aa2d005dd53 (patch)
treed8b66baa55842733ab88fb97fe4612ceda7f374a
parentdd99c29e83e48acf80ee1855a5a6991b3e6523f5 (diff)
net: ethernet: ti: am65-cpsw-nuss: Enable SGMII mode for J784S4 CPSW9G
TI's J784S4 SoC supports SGMII mode with CPSW9G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the extra_modes member of the "j784s4_cpswxg_pdata" SoC data. Reviewed-by: Roger Quadros <[email protected]> Signed-off-by: Chintan Vankar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
-rw-r--r--drivers/net/ethernet/ti/am65-cpsw-nuss.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
index 81a0fe1f1045..67b3a94e5efa 100644
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
@@ -3390,7 +3390,8 @@ static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = {
.quirks = 0,
.ale_dev_id = "am64-cpswxg",
.fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
- .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_USXGMII),
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
+ BIT(PHY_INTERFACE_MODE_USXGMII),
};
static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {