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authorPaul Cercueil <[email protected]>2019-05-08 00:43:57 +0200
committerPaul Burton <[email protected]>2019-07-21 15:23:24 -0700
commit368fb26c1e55a187131a794f95420d96d31d0e5e (patch)
treefa730e4917d920e082f2b1de4f50947b2787bedd
parent3b25b763116482596227225bea7c03fcde11c9ed (diff)
MIPS: Decode config3 register on Ingenic SoCs
XBurst misses a config2 register, so config3 decode was skipped in decode_configs(). Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
-rw-r--r--arch/mips/kernel/cpu-probe.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index fd77dbc29af9..a9c82338396a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1956,9 +1956,17 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
{
decode_configs(c);
+
+ /*
+ * XBurst misses a config2 register, so config3 decode was skipped in
+ * decode_configs().
+ */
+ decode_config3(c);
+
/* XBurst does not implement the CP0 counter. */
c->options &= ~MIPS_CPU_COUNTER;
BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
+
switch (c->processor_id & PRID_IMP_MASK) {
case PRID_IMP_XBURST:
c->cputype = CPU_XBURST;