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<title>blaster4385/linux-IllusionX/drivers/iio/dac/Makefile, branch v6.13</title>
<subtitle>Linux kernel with personal config changes for arch linux</subtitle>
<id>http://git.tablaster.dev/blaster4385/linux-IllusionX/atom?h=v6.13</id>
<link rel='self' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/atom?h=v6.13'/>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/'/>
<updated>2024-11-03T20:33:32Z</updated>
<entry>
<title>iio: dac: ad3552r: add high-speed platform driver</title>
<updated>2024-11-03T20:33:32Z</updated>
<author>
<name>Angelo Dureghello</name>
<email>adureghello@baylibre.com</email>
</author>
<published>2024-10-28T21:45:34Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=0b4d9fe58be8260819c453fb4717f23bdafd3ba3'/>
<id>urn:sha1:0b4d9fe58be8260819c453fb4717f23bdafd3ba3</id>
<content type='text'>
Add High Speed ad3552r platform driver.

The ad3552r DAC is controlled by a custom (fpga-based) DAC IP
through the current AXI backend, or similar alternative IIO backend.

Compared to the existing driver (ad3552r.c), that is a simple SPI
driver, this driver is coupled with a DAC IIO backend that finally
controls the ad3552r by a fpga-based "QSPI+DDR" interface, to reach
maximum transfer rate of 33MUPS using dma stream capabilities.

All commands involving QSPI bus read/write are delegated to the backend
through the provided APIs for bus read/write.

Reviewed-by: Nuno Sa &lt;nuno.sa@analog.com&gt;
Signed-off-by: Angelo Dureghello &lt;adureghello@baylibre.com&gt;
Reviewed-by: David Lechner &lt;dlechner@baylibre.com&gt;
Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-7-f6960b4f9719@kernel-space.org
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: ad3552r: extract common code (no changes in behavior intended)</title>
<updated>2024-11-01T14:54:48Z</updated>
<author>
<name>Angelo Dureghello</name>
<email>adureghello@baylibre.com</email>
</author>
<published>2024-10-28T21:45:33Z</published>
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<id>urn:sha1:f665d7d33d7909cf51e2db0f0767ecab0295c0bd</id>
<content type='text'>
Extracting common code, to share common code to be used later
by the AXI driver version (ad3552r-axi.c).

Signed-off-by: Angelo Dureghello &lt;adureghello@baylibre.com&gt;
Reviewed-by: David Lechner &lt;dlechner@baylibre.com&gt;
Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-6-f6960b4f9719@kernel-space.org
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: support the ad8460 Waveform DAC</title>
<updated>2024-09-30T08:21:03Z</updated>
<author>
<name>Mariel Tinaco</name>
<email>Mariel.Tinaco@analog.com</email>
</author>
<published>2024-09-12T09:54:35Z</published>
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<id>urn:sha1:a976ef24c62540d6dd166a93e474684ae5463455</id>
<content type='text'>
The AD8460 is a “bits in, power out” high voltage, high-power,
high-speed driver optimized for large output current (up to ±1 A)
and high slew rate (up to ±1800 V/μs) at high voltage (up to ±40 V)
into capacitive loads.

A digital engine implements user-configurable features: modes for
digital input, programmable supply current, and fault monitoring
and programmable protection settings for output current,
output voltage, and junction temperature. The AD8460 operates on
high voltage dual supplies up to ±55 V and a single low voltage
supply of 5 V.

Signed-off-by: Mariel Tinaco &lt;Mariel.Tinaco@analog.com&gt;
Link: https://patch.msgid.link/20240912095435.18639-3-Mariel.Tinaco@analog.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: ltc2664: Add driver for LTC2664 and LTC2672</title>
<updated>2024-08-03T09:13:37Z</updated>
<author>
<name>Kim Seer Paller</name>
<email>kimseer.paller@analog.com</email>
</author>
<published>2024-07-18T05:18:34Z</published>
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<id>urn:sha1:4cc2fc445d2e4e63ed6bd5d310752d88d365f8e4</id>
<content type='text'>
LTC2664 4 channel, 12-/16-Bit Voltage Output SoftSpan DAC
LTC2672 5 channel, 12-/16-Bit Current Output Softspan DAC

Reviewed-by: Nuno Sa &lt;nuno.sa@analog.com&gt;
Co-developed-by: Michael Hennerich &lt;michael.hennerich@analog.com&gt;
Signed-off-by: Michael Hennerich &lt;michael.hennerich@analog.com&gt;
Signed-off-by: Kim Seer Paller &lt;kimseer.paller@analog.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://patch.msgid.link/20240718051834.32270-7-kimseer.paller@analog.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: support the ad9739a RF DAC</title>
<updated>2024-04-20T14:41:32Z</updated>
<author>
<name>Nuno Sa</name>
<email>nuno.sa@analog.com</email>
</author>
<published>2024-04-19T08:25:43Z</published>
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<id>urn:sha1:e77603d5468b9093c111a998a86604e21a9e7f48</id>
<content type='text'>
The AD9739A is a 14-bit, 2.5 GSPS high performance RF DACs that are capable
of synthesizing wideband signals from DC up to 3 GHz.

A dual-port, source synchronous, LVDS interface simplifies the digital
interface with existing FGPA/ASIC technology. On-chip controllers are used
to manage external and internal clock domain variations over temperature to
ensure reliable data transfer from the host to the DAC core.

Co-developed-by: Dragos Bogdan &lt;dragos.bogdan@analog.com&gt;
Signed-off-by: Dragos Bogdan &lt;dragos.bogdan@analog.com&gt;
Signed-off-by: Nuno Sa &lt;nuno.sa@analog.com&gt;
Link: https://lore.kernel.org/r/20240419-iio-backend-axi-dac-v4-10-5ca45b4de294@analog.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: add support for AXI DAC IP core</title>
<updated>2024-04-20T14:41:32Z</updated>
<author>
<name>Nuno Sa</name>
<email>nuno.sa@analog.com</email>
</author>
<published>2024-04-19T08:25:42Z</published>
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<id>urn:sha1:4e3949a192e45a8e3543dbdbc853b90c3c25692e</id>
<content type='text'>
Support the Analog Devices Generic AXI DAC IP core. The IP core is used
for interfacing with digital-to-analog (DAC) converters that require either
a high-speed serial interface (JESD204B/C) or a source synchronous parallel
interface (LVDS/CMOS). Typically (for such devices) SPI will be used for
configuration only, while this IP core handles the streaming of data into
memory via DMA.

Signed-off-by: Nuno Sa &lt;nuno.sa@analog.com&gt;
Link: https://lore.kernel.org/r/20240419-iio-backend-axi-dac-v4-9-5ca45b4de294@analog.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: driver for MCP4821</title>
<updated>2023-12-21T17:04:42Z</updated>
<author>
<name>Anshul Dalal</name>
<email>anshulusr@gmail.com</email>
</author>
<published>2023-12-20T15:19:53Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=cdf3ecb0d8d0a83c940a8892b3e8aeaf35dc4353'/>
<id>urn:sha1:cdf3ecb0d8d0a83c940a8892b3e8aeaf35dc4353</id>
<content type='text'>
Adds driver for the MCP48xx series of DACs.

Device uses a simplex SPI channel. To set the value of an output channel,
a 16-bit data of following format must be written:

Bit field | Description
15 [MSB]  | Channel selection bit
            0 -&gt; Channel A
            1 -&gt; Channel B
13        | Output Gain Selection bit
            0 -&gt; 2x Gain (Vref = 4.096V)
            1 -&gt; 1x Gain (Vref = 2.048V)
12        | Output Shutdown Control bit
            0 -&gt; Shutdown the selected channel
            1 -&gt; Active mode operation
11-0 [LSB]| DAC Input Data bits
            Value's big endian representation is taken as input for the
            selected DAC channel. For devices with a resolution of less
            than 12-bits, only the x most significant bits are considered
            where x is the resolution of the device.
Reference: Page#22 [MCP48x2 Datasheet]

Supported devices:
  +---------+--------------+-------------+
  | Device  |  Resolution  |   Channels  |
  |---------|--------------|-------------|
  | MCP4801 |     8-bit    |      1      |
  | MCP4802 |     8-bit    |      2      |
  | MCP4811 |    10-bit    |      1      |
  | MCP4812 |    10-bit    |      2      |
  | MCP4821 |    12-bit    |      1      |
  | MCP4822 |    12-bit    |      2      |
  +---------+--------------+-------------+

Devices tested:
  MCP4821 [12-bit single channel]
  MCP4802 [8-bit dual channel]

Tested on Raspberry Pi Zero 2W

Datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22244B.pdf #MCP48x1
Datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/20002249B.pdf #MCP48x2
Signed-off-by: Anshul Dalal &lt;anshulusr@gmail.com&gt;
Link: https://lore.kernel.org/r/20231220151954.154595-2-anshulusr@gmail.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: add MCP4728 I2C DAC driver</title>
<updated>2023-08-05T18:29:39Z</updated>
<author>
<name>Andrea Collamati</name>
<email>andrea.collamati@gmail.com</email>
</author>
<published>2023-08-03T12:56:35Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=7b24a034ad90730b2c7bb9670d0eadcdcb5d59d2'/>
<id>urn:sha1:7b24a034ad90730b2c7bb9670d0eadcdcb5d59d2</id>
<content type='text'>
MCP4728 is a 12-bit quad channel DAC with I2C interface.

support for:
 * per-channel gain
 * per-channel power state
 * per-channel power down mode control
 * per-channel vref selection internal/vdd
 * store current state to on-chip EEPROM

Signed-off-by: Andrea Collamati &lt;andrea.collamati@gmail.com&gt;
Link: https://lore.kernel.org/r/a0933003ed3c855f9d80d6ce0a40add2b6f0ba36.1691066050.git.andrea.collamati@gmail.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: build ad5758 driver when AD5758 is selected</title>
<updated>2023-05-13T18:18:11Z</updated>
<author>
<name>Lukas Bulwahn</name>
<email>lukas.bulwahn@gmail.com</email>
</author>
<published>2023-05-08T04:02:08Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=a146eccb68be161ae9eab5f3f68bb0ed7c0fbaa8'/>
<id>urn:sha1:a146eccb68be161ae9eab5f3f68bb0ed7c0fbaa8</id>
<content type='text'>
Commit 28d1a7ac2a0d ("iio: dac: Add AD5758 support") adds the config AD5758
and the corresponding driver ad5758.c. In the Makefile, the ad5758 driver
is however included when AD5755 is selected, not when AD5758 is selected.

Probably, this was simply a mistake that happened by copy-and-paste and
forgetting to adjust the actual line. Surprisingly, no one has ever noticed
that this driver is actually only included when AD5755 is selected and that
the config AD5758 has actually no effect on the build.

Fixes: 28d1a7ac2a0d ("iio: dac: Add AD5758 support")
Signed-off-by: Lukas Bulwahn &lt;lukas.bulwahn@gmail.com&gt;
Link: https://lore.kernel.org/r/20230508040208.12033-1-lukas.bulwahn@gmail.com
Cc: &lt;Stable@vger.kernel.org&gt;
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: add support for max5522</title>
<updated>2023-01-21T17:58:59Z</updated>
<author>
<name>Angelo Dureghello</name>
<email>angelo.dureghello@timesys.com</email>
</author>
<published>2022-11-06T16:59:28Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=ba56b46d1c6d412ae8c079e67c01a1f7bbd5c079'/>
<id>urn:sha1:ba56b46d1c6d412ae8c079e67c01a1f7bbd5c079</id>
<content type='text'>
Add initial support for DAC max5522.

Tested writing DAC A and B with some values,
from 0 to 1023, measured output voltages, driver works properly.

Additions for max5523/24/25 will follow.

Signed-off-by: Angelo Dureghello &lt;angelo.dureghello@timesys.com&gt;
Link: https://lore.kernel.org/r/20221106165928.223318-1-angelo.dureghello@timesys.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
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