blaster4385/linux-IllusionX/drivers/gpu/drm/amd/include, branch v6.12.10Linux kernel with personal config changes for arch linuxhttps://git.tablaster.dev/blaster4385/linux-IllusionX/atom?h=v6.12.102024-12-09T09:41:14Zdrm/amd: Add some missing straps from NBIO 7.11.02024-12-09T09:41:14ZMario Limonciellomario.limonciello@amd.com2024-11-18T17:46:10Zurn:sha1:be51376b1f500f455d7403590b5e617f2f1444cd
commit 902fbbf429b8213232b18de0ddfd5c0f3851cb8f upstream.
Earlier ASICs have strap information exported, and this is missing
for NBIO 7.11.0.
Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Fixes: ca8c68142ad8 ("drm/amdgpu: add nbio 7.11 registers")
Link: https://lore.kernel.org/r/20241118174611.10700-1-mario.limonciello@amd.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amdkfd: Update logic for CU occupancy calculations2024-09-25T16:56:00ZMukul Joshimukul.joshi@amd.com2024-09-16T18:33:58Zurn:sha1:6ae9e1aba97e4cdaa31a0bfdc07497ad0e915c84
Currently, the code uses the IH_VMID_X_LUT register to map
a queue's vmid to the corresponding PASID. This logic is racy
since CP can update the VMID-PASID mapping anytime especially
when there are more processes than number of vmids. Update the
logic to calculate CU occupancy by matching doorbell offset of
the queue with valid wave counts against the process's queues.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: fix spelling in amd_shared.h2024-09-18T20:14:26ZAlex Deucheralexander.deucher@amd.com2024-09-10T14:19:43Zurn:sha1:902b4027216aeaabe1562e1db070550c06f3ec89
Fix spelling in documentation.
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/atomfirmware: Silence UBSAN warning2024-09-10T17:44:29ZAlex Deucheralexander.deucher@amd.com2024-09-06T14:42:45Zurn:sha1:81f7804ba84ee617ed594de934ed87bcc4f83531
Per the comments, these are variable sized arrays.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3613
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Introduce additional IPS debug flags2024-08-27T21:51:32ZLeo Lisunpeng.li@amd.com2024-08-06T17:29:13Zurn:sha1:a08d75927f99e57c793f3a5d11260c22893fc0e9
[Why]
Idle power states (IPS) describe levels of power-gating within DCN. DM
and DC is responsible for ensuring that we are out of IPS before any DCN
programming happens. Any DCN programming while we're in IPS leads to
undefined behavior (mostly hangs).
Because IPS intersects with all display features, the ability to disable
IPS by default while ironing out the known issues is desired. However,
disabing it completely will cause important features such as s0ix entry
to fail.
Therefore, more granular IPS debug flags are desired.
[How]
Extend the dc debug mask bits to include the available list of IPS
debug flags.
All the flags should work as documented, with the exception of
IPS_DISABLE_DYNAMIC. It requires dm changes which will be done in
later changes.
v2: enable docs and fix docstring format
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: support for gc_info table v1.32024-08-23T14:54:57ZLikun GaoLikun.Gao@amd.com2024-08-22T03:44:12Zurn:sha1:875ff9a7ee8824200885384effa7743892a34ed6
Add gc_info table v1.3 for IP discovery.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Disable dpm_enabled flag while VF is in reset2024-08-13T16:12:52ZVictor Skvortsovvictor.skvortsov@amd.com2024-08-08T17:22:34Zurn:sha1:f83cec3b3a7c968bbceb810b7acd1baf3fe8cd87
VFs do not perform HW fini/suspend in FLR, so the dpm_enabled
is incorrectly kept enabled. Add interface to disable it in
virt_pre_reset call.
v2: Made implementation generic for all asics
v3: Re-order conditionals so PP_MP1_STATE_FLR is only evaluated on VF
Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/mes12: update mes_v12_api_def.h2024-08-13T14:29:18ZJack XiaoJack.Xiao@amd.com2024-08-07T03:43:45Zurn:sha1:2ab5dc59177419d8a49e89585e82ff41524270fc
Update mes12 api definition.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/uvd4: fix mask and shift definitions2024-08-13T14:26:48ZRemington Brasgarbrasga@uci.edu2024-07-31T05:54:51Zurn:sha1:3834ce360067b4ee98fdef14571923500a0499a4
A few define's are listed twice with different, incorrect values.
This fix sets them appropriately.
Signed-off-by: Remington Brasga <rbrasga@uci.edu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdkfd: support per-queue reset on gfx92024-08-06T14:43:18ZJonathan KimJonathan.Kim@amd.com2024-06-25T15:22:50Zurn:sha1:ee0a469cf9175aeb6131c0476c4a4a8eb5997dfa
Support per-queue reset for GFX9. The recommendation is for the driver
to target reset the HW queue via a SPI MMIO register write.
Since this requires pipe and HW queue info and MEC FW is limited to
doorbell reports of hung queues after an unmap failure, scan the HW
queue slots defined by SET_RESOURCES first to identify the user queue
candidates to reset.
Only signal reset events to processes that have had a queue reset.
If queue reset fails, fall back to GPU reset.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>