blaster4385/linux-IllusionX/drivers/gpu/drm/amd/include, branch v6.12.1

drm/amdkfd: Update logic for CU occupancy calculations

2024-09-25T16:56:00Z

Currently, the code uses the IH_VMID_X_LUT register to map a queue's vmid to the corresponding PASID. This logic is racy since CP can update the VMID-PASID mapping anytime especially when there are more processes than number of vmids. Update the logic to calculate CU occupancy by matching doorbell offset of the queue with valid wave counts against the process's queues. Signed-off-by: Mukul Joshi Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alex Deucher

drm/amdgpu: fix spelling in amd_shared.h

2024-09-18T20:14:26Z

Fix spelling in documentation. Reviewed-by: Kent Russell Signed-off-by: Alex Deucher

drm/amdgpu/atomfirmware: Silence UBSAN warning

2024-09-10T17:44:29Z

Per the comments, these are variable sized arrays. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3613 Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd: Introduce additional IPS debug flags

2024-08-27T21:51:32Z

[Why] Idle power states (IPS) describe levels of power-gating within DCN. DM and DC is responsible for ensuring that we are out of IPS before any DCN programming happens. Any DCN programming while we're in IPS leads to undefined behavior (mostly hangs). Because IPS intersects with all display features, the ability to disable IPS by default while ironing out the known issues is desired. However, disabing it completely will cause important features such as s0ix entry to fail. Therefore, more granular IPS debug flags are desired. [How] Extend the dc debug mask bits to include the available list of IPS debug flags. All the flags should work as documented, with the exception of IPS_DISABLE_DYNAMIC. It requires dm changes which will be done in later changes. v2: enable docs and fix docstring format Signed-off-by: Leo Li Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amdgpu: support for gc_info table v1.3

2024-08-23T14:54:57Z

Add gc_info table v1.3 for IP discovery. Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: Disable dpm_enabled flag while VF is in reset

2024-08-13T16:12:52Z

VFs do not perform HW fini/suspend in FLR, so the dpm_enabled is incorrectly kept enabled. Add interface to disable it in virt_pre_reset call. v2: Made implementation generic for all asics v3: Re-order conditionals so PP_MP1_STATE_FLR is only evaluated on VF Signed-off-by: Victor Skvortsov Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amdgpu/mes12: update mes_v12_api_def.h

2024-08-13T14:29:18Z

Update mes12 api definition. Signed-off-by: Jack Xiao Acked-by: Alex Deucher Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu/uvd4: fix mask and shift definitions

2024-08-13T14:26:48Z

A few define's are listed twice with different, incorrect values. This fix sets them appropriately. Signed-off-by: Remington Brasga Signed-off-by: Alex Deucher

drm/amdkfd: support per-queue reset on gfx9

2024-08-06T14:43:18Z

Support per-queue reset for GFX9. The recommendation is for the driver to target reset the HW queue via a SPI MMIO register write. Since this requires pipe and HW queue info and MEC FW is limited to doorbell reports of hung queues after an unmap failure, scan the HW queue slots defined by SET_RESOURCES first to identify the user queue candidates to reset. Only signal reset events to processes that have had a queue reset. If queue reset fails, fall back to GPU reset. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: increase mes log buffer size for gfx12

2024-07-27T21:32:05Z

MES firmware requires larger log buffer for gfx12. Allocate proper buffer respectively for gfx11 and gfx12. Signed-off-by: Michael Chen Acked-by: Alex Deucher Signed-off-by: Alex Deucher