<feed xmlns='http://www.w3.org/2005/Atom'>
<title>blaster4385/linux-IllusionX/drivers/gpu/drm/amd/display/dc/dml2/dml21/src, branch v6.12.1</title>
<subtitle>Linux kernel with personal config changes for arch linux</subtitle>
<id>http://git.tablaster.dev/blaster4385/linux-IllusionX/atom?h=v6.12.1</id>
<link rel='self' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/atom?h=v6.12.1'/>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/'/>
<updated>2024-11-11T19:05:26Z</updated>
<entry>
<title>drm/amd/display: Require minimum VBlank size for stutter optimization</title>
<updated>2024-11-11T19:05:26Z</updated>
<author>
<name>Dillon Varone</name>
<email>dillon.varone@amd.com</email>
</author>
<published>2024-11-01T16:00:14Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=9fc0cbcb6e45d6fc96ffd3bb7b6d6d28d693ff4d'/>
<id>urn:sha1:9fc0cbcb6e45d6fc96ffd3bb7b6d6d28d693ff4d</id>
<content type='text'>
If the nominal VBlank is too small, optimizing for stutter can cause
the prefetch bandwidth to increase drasticaly, resulting in higher
clock and power requirements. Only optimize if it is &gt;3x the stutter
latency.

Reviewed-by: Austin Zheng &lt;austin.zheng@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 003215f962cdf2265f126a3f4c9ad20917f87fca)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: Block timing sync for different output formats in pmo</title>
<updated>2024-09-18T20:15:07Z</updated>
<author>
<name>Dillon Varone</name>
<email>dillon.varone@amd.com</email>
</author>
<published>2024-08-26T21:08:33Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=0765b2afc1118a6ab5fee624e206c782d70db28a'/>
<id>urn:sha1:0765b2afc1118a6ab5fee624e206c782d70db28a</id>
<content type='text'>
[WHY &amp; HOW]
If the output format is different for HDMI TMDS signals, they are not
synchronizable.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Block timing sync for different signals in PMO</title>
<updated>2024-09-02T15:39:14Z</updated>
<author>
<name>Dillon Varone</name>
<email>dillon.varone@amd.com</email>
</author>
<published>2024-08-22T21:52:57Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=29d3d6af43135de7bec677f334292ca8dab53d67'/>
<id>urn:sha1:29d3d6af43135de7bec677f334292ca8dab53d67</id>
<content type='text'>
PMO assumes that like timings can be synchronized, but DC only allows
this if the signal types match.

Reviewed-by: Austin Zheng &lt;austin.zheng@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Resolve Coverity Issues</title>
<updated>2024-08-27T21:52:15Z</updated>
<author>
<name>Daniel Sa</name>
<email>Daniel.Sa@amd.com</email>
</author>
<published>2024-08-12T19:24:27Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=6dcc304f85898b099b35c63748c5e11ba56d0c8a'/>
<id>urn:sha1:6dcc304f85898b099b35c63748c5e11ba56d0c8a</id>
<content type='text'>
[WHY]
Remove coverity issues that were originally ignored.

[HOW]
Ran coverity locally on driver, used output report to find existing
coverity issues, resolved them

Reviewed-by: Nicholas Choi &lt;nicholas.choi@amd.com&gt;
Signed-off-by: Daniel Sa &lt;Daniel.Sa@amd.com&gt;
Signed-off-by: Zaeem Mohamed &lt;zaeem.mohamed@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix MS/MP mismatches in dml21 for dcn401</title>
<updated>2024-08-27T21:52:07Z</updated>
<author>
<name>Dillon Varone</name>
<email>dillon.varone@amd.com</email>
</author>
<published>2024-08-14T21:32:16Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=949237a34dba3f0218857f5afa0dde2076dd8c82'/>
<id>urn:sha1:949237a34dba3f0218857f5afa0dde2076dd8c82</id>
<content type='text'>
[WHY]
Prefetch calculations did not guarantee that bandwidth required in
mode support was less than mode programming which can cause failures.

[HOW]
Fix bandwidth calculations to assume fixed times for OTO schedule,
and choose which schedule to use based on time to fetch pixel data.

Reviewed-by: Jun Lei &lt;jun.lei@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Zaeem Mohamed &lt;zaeem.mohamed@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Make core_dcn4_ip_caps_base static</title>
<updated>2024-08-23T14:53:36Z</updated>
<author>
<name>Jinjie Ruan</name>
<email>ruanjinjie@huawei.com</email>
</author>
<published>2024-08-21T06:40:37Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=0e405395e0b162075001b9c027443dd10b723a03'/>
<id>urn:sha1:0e405395e0b162075001b9c027443dd10b723a03</id>
<content type='text'>
The sparse tool complains as follows:

drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c:12:28: warning:
	symbol 'core_dcn4_ip_caps_base' was not declared. Should it be static?

This symbol is not used outside of dcn35_hubp.c, so marks it static.

And do not want to change it, so mark it const.

Signed-off-by: Jinjie Ruan &lt;ruanjinjie@huawei.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Make core_dcn4_g6_temp_read_blackout_table static</title>
<updated>2024-08-23T14:53:31Z</updated>
<author>
<name>Jinjie Ruan</name>
<email>ruanjinjie@huawei.com</email>
</author>
<published>2024-08-21T06:40:36Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=988bfa0bc67d7220ff8d9e2ba3a425727aa98af3'/>
<id>urn:sha1:988bfa0bc67d7220ff8d9e2ba3a425727aa98af3</id>
<content type='text'>
The sparse tool complains as follows:

drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:6853:56: warning:
	symbol 'core_dcn4_g6_temp_read_blackout_table' was not declared. Should it be static?

This symbol is not used outside of dml2_core_dcn4_calcs.c, so marks it static.

And not want to change it, so mark it const.

Signed-off-by: Jinjie Ruan &lt;ruanjinjie@huawei.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: DML2.1 Reintegration for Various Fixes</title>
<updated>2024-08-21T02:14:14Z</updated>
<author>
<name>Austin Zheng</name>
<email>Austin.Zheng@amd.com</email>
</author>
<published>2024-08-15T22:45:23Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=d07722e1fc749fbd78992650b6d00c9a2619be70'/>
<id>urn:sha1:d07722e1fc749fbd78992650b6d00c9a2619be70</id>
<content type='text'>
[Why and How]
DML2.1 reintegration for several fixes and updates to the DML
code.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Austin Zheng &lt;Austin.Zheng@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: apply vmin optimization even if it doesn't reach vmin level</title>
<updated>2024-08-13T14:31:47Z</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2024-05-31T15:37:15Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=782cef7fc367542ccc851d93edbed166defdfc27'/>
<id>urn:sha1:782cef7fc367542ccc851d93edbed166defdfc27</id>
<content type='text'>
[why]
Based on power measurement result, in most cases when display clock
is higher than Vmin display clock, lowering display clock using
dynamic ODM will improve overall power consumption by 0 to 4 watts
even if we can't reach Vmin.

[how]
Allow vmin optimization applied even if dispclk can't reach Vmin.

Reviewed-by: Austin Zheng &lt;austin.zheng@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix minor coding errors where dml21 phase 5 uses wrong variables</title>
<updated>2024-08-13T14:31:40Z</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2024-05-27T14:30:45Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=596a4ec72876f1061f0ef4be47076b093f03b4f9'/>
<id>urn:sha1:596a4ec72876f1061f0ef4be47076b093f03b4f9</id>
<content type='text'>
[why &amp; how]
There is a coding error which causes incorrect variables to be assigned
in DML21 phase 5.

Reviewed-by: Austin Zheng &lt;austin.zheng@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
