<feed xmlns='http://www.w3.org/2005/Atom'>
<title>blaster4385/linux-IllusionX/arch/x86/kernel/cpu/mtrr, branch v6.13</title>
<subtitle>Linux kernel with personal config changes for arch linux</subtitle>
<id>http://git.tablaster.dev/blaster4385/linux-IllusionX/atom?h=v6.13</id>
<link rel='self' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/atom?h=v6.13'/>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/'/>
<updated>2024-08-22T18:25:46Z</updated>
<entry>
<title>x86/cpu: KVM: Add common defines for architectural memory types (PAT, MTRRs, etc.)</title>
<updated>2024-08-22T18:25:46Z</updated>
<author>
<name>Sean Christopherson</name>
<email>seanjc@google.com</email>
</author>
<published>2024-06-05T23:19:09Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=e7e80b66fb242a63cdfc3d3534cff62a5e293185'/>
<id>urn:sha1:e7e80b66fb242a63cdfc3d3534cff62a5e293185</id>
<content type='text'>
Add defines for the architectural memory types that can be shoved into
various MSRs and registers, e.g. MTRRs, PAT, VMX capabilities MSRs, EPTPs,
etc.  While most MSRs/registers support only a subset of all memory types,
the values themselves are architectural and identical across all users.

Leave the goofy MTRR_TYPE_* definitions as-is since they are in a uapi
header, but add compile-time assertions to connect the dots (and sanity
check that the msr-index.h values didn't get fat-fingered).

Keep the VMX_EPTP_MT_* defines so that it's slightly more obvious that the
EPTP holds a single memory type in 3 of its 64 bits; those bits just
happen to be 2:0, i.e. don't need to be shifted.

Opportunistically use X86_MEMTYPE_WB instead of an open coded '6' in
setup_vmcs_config().

No functional change intended.

Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Kai Huang &lt;kai.huang@intel.com&gt;
Reviewed-by: Xiaoyao Li &lt;xiaoyao.li@intel.com&gt;
Reviewed-by: Kai Huang &lt;kai.huang@intel.com&gt;
Link: https://lore.kernel.org/r/20240605231918.2915961-2-seanjc@google.com
Signed-off-by: Sean Christopherson &lt;seanjc@google.com&gt;
</content>
</entry>
<entry>
<title>x86/mtrr: Check if fixed MTRRs exist before saving them</title>
<updated>2024-08-08T15:03:12Z</updated>
<author>
<name>Andi Kleen</name>
<email>ak@linux.intel.com</email>
</author>
<published>2024-08-08T00:02:44Z</published>
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<id>urn:sha1:919f18f961c03d6694aa726c514184f2311a4614</id>
<content type='text'>
MTRRs have an obsolete fixed variant for fine grained caching control
of the 640K-1MB region that uses separate MSRs. This fixed variant has
a separate capability bit in the MTRR capability MSR.

So far all x86 CPUs which support MTRR have this separate bit set, so it
went unnoticed that mtrr_save_state() does not check the capability bit
before accessing the fixed MTRR MSRs.

Though on a CPU that does not support the fixed MTRR capability this
results in a #GP.  The #GP itself is harmless because the RDMSR fault is
handled gracefully, but results in a WARN_ON().

Add the missing capability check to prevent this.

Fixes: 2b1f6278d77c ("[PATCH] x86: Save the MTRRs of the BSP before booting an AP")
Signed-off-by: Andi Kleen &lt;ak@linux.intel.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/all/20240808000244.946864-1-ak@linux.intel.com
</content>
</entry>
<entry>
<title>x86/CPU/AMD: Track SNP host status with cc_platform_*()</title>
<updated>2024-04-04T08:40:30Z</updated>
<author>
<name>Borislav Petkov (AMD)</name>
<email>bp@alien8.de</email>
</author>
<published>2024-03-27T15:43:17Z</published>
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<id>urn:sha1:0ecaefb303de69929dc0036d5021d01cec7ea052</id>
<content type='text'>
The host SNP worthiness can determined later, after alternatives have
been patched, in snp_rmptable_init() depending on cmdline options like
iommu=pt which is incompatible with SNP, for example.

Which means that one cannot use X86_FEATURE_SEV_SNP and will need to
have a special flag for that control.

Use that newly added CC_ATTR_HOST_SEV_SNP in the appropriate places.

Move kdump_sev_callback() to its rightful place, while at it.

Fixes: 216d106c7ff7 ("x86/sev: Add SEV-SNP host initialization support")
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Reviewed-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Tested-by: Srikanth Aithal &lt;sraithal@amd.com&gt;
Link: https://lore.kernel.org/r/20240327154317.29909-6-bp@alien8.de
</content>
</entry>
<entry>
<title>x86/mtrr: Don't print errors if MtrrFixDramModEn is set when SNP enabled</title>
<updated>2024-01-29T16:24:27Z</updated>
<author>
<name>Ashish Kalra</name>
<email>ashish.kalra@amd.com</email>
</author>
<published>2024-01-26T04:11:05Z</published>
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<id>urn:sha1:e3fd08afb7c350d5612f113eadfb4ebb6ed08deb</id>
<content type='text'>
SNP enabled platforms require the MtrrFixDramModeEn bit to be set across
all CPUs when SNP is enabled. Therefore, don't print error messages when
MtrrFixDramModeEn is set when bringing CPUs online.

Closes: https://lore.kernel.org/kvm/68b2d6bf-bce7-47f9-bebb-2652cc923ff9@linux.microsoft.com/
Reported-by: Jeremi Piotrowski &lt;jpiotrowski@linux.microsoft.com&gt;
Signed-off-by: Ashish Kalra &lt;ashish.kalra@amd.com&gt;
Signed-off-by: Michael Roth &lt;michael.roth@amd.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Link: https://lore.kernel.org/r/20240126041126.1927228-6-michael.roth@amd.com
</content>
</entry>
<entry>
<title>x86/mtrr: Document missing function parameters in kernel-doc</title>
<updated>2023-11-20T09:19:27Z</updated>
<author>
<name>Borislav Petkov (AMD)</name>
<email>bp@alien8.de</email>
</author>
<published>2023-11-13T13:52:52Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=4e15b91c5b7919c530c27f39c7f2d392bf0a95e3'/>
<id>urn:sha1:4e15b91c5b7919c530c27f39c7f2d392bf0a95e3</id>
<content type='text'>
Add text explaining what they do.

No functional changes.

Closes: https://lore.kernel.org/oe-kbuild-all/202311130104.9xKAKzke-lkp@intel.com/
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Link: https://lore.kernel.org/r/202311130104.9xKAKzke-lkp@intel.com
</content>
</entry>
<entry>
<title>x86/mtrr: Unify debugging printing</title>
<updated>2023-06-01T13:04:33Z</updated>
<author>
<name>Borislav Petkov (AMD)</name>
<email>bp@alien8.de</email>
</author>
<published>2023-05-31T17:23:34Z</published>
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<id>urn:sha1:7c1dee734f3b8003429c40fb9186401485670dfd</id>
<content type='text'>
Put all the debugging output behind "mtrr=debug" and get rid of
"mtrr_cleanup_debug" which wasn't even documented anywhere.

No functional changes.

Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Reviewed-by: Juergen Gross &lt;jgross@suse.com&gt;
Link: https://lore.kernel.org/r/20230531174857.GDZHeIib57h5lT5Vh1@fat_crate.local
</content>
</entry>
<entry>
<title>x86/mtrr: Remove unused code</title>
<updated>2023-06-01T13:04:33Z</updated>
<author>
<name>Juergen Gross</name>
<email>jgross@suse.com</email>
</author>
<published>2023-05-02T12:09:31Z</published>
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<id>urn:sha1:08611a3a9a23e5e2e1a799e966c69ebc4851dfa8</id>
<content type='text'>
mtrr_centaur_report_mcr() isn't used by anyone, so it can be removed.

Signed-off-by: Juergen Gross &lt;jgross@suse.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Tested-by: Michael Kelley &lt;mikelley@microsoft.com&gt;
Link: https://lore.kernel.org/r/20230502120931.20719-17-jgross@suse.com
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
</content>
</entry>
<entry>
<title>x86/mtrr: Don't let mtrr_type_lookup() return MTRR_TYPE_INVALID</title>
<updated>2023-06-01T13:04:33Z</updated>
<author>
<name>Juergen Gross</name>
<email>jgross@suse.com</email>
</author>
<published>2023-05-02T12:09:29Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=973df1942068c0cc72244ce7dce5e5aeca03ad5f'/>
<id>urn:sha1:973df1942068c0cc72244ce7dce5e5aeca03ad5f</id>
<content type='text'>
mtrr_type_lookup() should always return a valid memory type. In case
there is no information available, it should return the default UC.

This will remove the last case where mtrr_type_lookup() can return
MTRR_TYPE_INVALID, so adjust the comment in include/uapi/asm/mtrr.h.

Note that removing the MTRR_TYPE_INVALID #define from that header
could break user code, so it has to stay.

At the same time the mtrr_type_lookup() stub for the !CONFIG_MTRR
case should set uniform to 1, as if the memory range would be
covered by no MTRR at all.

Suggested-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Signed-off-by: Juergen Gross &lt;jgross@suse.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Tested-by: Michael Kelley &lt;mikelley@microsoft.com&gt;
Link: https://lore.kernel.org/r/20230502120931.20719-15-jgross@suse.com
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
</content>
</entry>
<entry>
<title>x86/mtrr: Use new cache_map in mtrr_type_lookup()</title>
<updated>2023-06-01T13:04:33Z</updated>
<author>
<name>Juergen Gross</name>
<email>jgross@suse.com</email>
</author>
<published>2023-05-02T12:09:28Z</published>
<link rel='alternate' type='text/html' href='http://git.tablaster.dev/blaster4385/linux-IllusionX/commit/?id=8227f40ade2362982505f66f1614b78a3a083ec9'/>
<id>urn:sha1:8227f40ade2362982505f66f1614b78a3a083ec9</id>
<content type='text'>
Instead of crawling through the MTRR register state, use the new
cache_map for looking up the cache type(s) of a memory region.

This allows now to set the uniform parameter according to the
uniformity of the cache mode of the region, instead of setting it
only if the complete region is mapped by a single MTRR. This now
includes even the region covered by the fixed MTRR registers.

Make sure uniform is always set.

  [ bp: Massage. ]

  [ jgross: Explain mtrr_type_lookup() logic. ]

Signed-off-by: Juergen Gross &lt;jgross@suse.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Tested-by: Michael Kelley &lt;mikelley@microsoft.com&gt;
Link: https://lore.kernel.org/r/20230502120931.20719-14-jgross@suse.com
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
</content>
</entry>
<entry>
<title>x86/mtrr: Add mtrr=debug command line option</title>
<updated>2023-06-01T13:04:33Z</updated>
<author>
<name>Juergen Gross</name>
<email>jgross@suse.com</email>
</author>
<published>2023-05-02T12:09:27Z</published>
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<id>urn:sha1:a4316603534cf7f4dcd9f9f1ed170257b987cca9</id>
<content type='text'>
Add a new command line option "mtrr=debug" for getting debug output
after building the new cache mode map. The output will include MTRR
register values and the resulting map.

Signed-off-by: Juergen Gross &lt;jgross@suse.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Tested-by: Michael Kelley &lt;mikelley@microsoft.com&gt;
Link: https://lore.kernel.org/r/20230502120931.20719-13-jgross@suse.com
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
</content>
</entry>
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