1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
184 lines
7.5 KiB
Text
184 lines
7.5 KiB
Text
Amiga 4-joystick parport extension
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Parallel port pins:
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(2) - Up1 (6) - Up2
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(3) - Down1 (7) - Down2
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(4) - Left1 (8) - Left2
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(5) - Right1 (9) - Right2
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(13) - Fire1 (11) - Fire2
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(18) - Gnd1 (18) - Gnd2
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Amiga digital joystick pinout
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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(1) - Up
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(2) - Down
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(3) - Left
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(4) - Right
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(5) - n/c
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(6) - Fire button
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(7) - +5V (50mA)
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(8) - Gnd
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(9) - Thumb button
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Amiga mouse pinout
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~~~~~~~~~~~~~~~~~~
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(1) - V-pulse
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(2) - H-pulse
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(3) - VQ-pulse
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(4) - HQ-pulse
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(5) - Middle button
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(6) - Left button
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(7) - +5V (50mA)
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(8) - Gnd
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(9) - Right button
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Amiga analog joystick pinout
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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(1) - Top button
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(2) - Top2 button
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(3) - Trigger button
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(4) - Thumb button
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(5) - Analog X
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(6) - n/c
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(7) - +5V (50mA)
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(8) - Gnd
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(9) - Analog Y
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Amiga lightpen pinout
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~~~~~~~~~~~~~~~~~~~~~
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(1) - n/c
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(2) - n/c
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(3) - n/c
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(4) - n/c
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(5) - Touch button
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(6) - /Beamtrigger
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(7) - +5V (50mA)
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(8) - Gnd
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(9) - Stylus button
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-------------------------------------------------------------------------------
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NAME rev ADDR type chip Description
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JOY0DAT 00A R Denise Joystick-mouse 0 data (left vert, horiz)
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JOY1DAT 00C R Denise Joystick-mouse 1 data (right vert,horiz)
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These addresses each read a 16 bit register. These in turn
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are loaded from the MDAT serial stream and are clocked in on
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the rising edge of SCLK. MLD output is used to parallel load
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the external parallel-to-serial converter.This in turn is
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loaded with the 4 quadrature inputs from each of two game
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controller ports (8 total) plus 8 miscellaneous control bits
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which are new for LISA and can be read in upper 8 bits of
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LISAID.
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Register bits are as follows:
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Mouse counter usage (pins 1,3 =Yclock, pins 2,4 =Xclock)
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BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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JOY0DAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
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JOY1DAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
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0=LEFT CONTROLLER PAIR, 1=RIGHT CONTROLLER PAIR.
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(4 counters total).The bit usage for both left and right
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addresses is shown below. Each 6 bit counter (Y7-Y2,X7-X2) is
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clocked by 2 of the signals input from the mouse serial
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stream. Starting with first bit recived:
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+-------------------+-----------------------------------------+
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| Serial | Bit Name | Description |
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+--------+----------+-----------------------------------------+
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| 0 | M0H | JOY0DAT Horizontal Clock |
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| 1 | M0HQ | JOY0DAT Horizontal Clock (quadrature) |
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| 2 | M0V | JOY0DAT Vertical Clock |
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| 3 | M0VQ | JOY0DAT Vertical Clock (quadrature) |
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| 4 | M1V | JOY1DAT Horizontall Clock |
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| 5 | M1VQ | JOY1DAT Horizontall Clock (quadrature) |
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| 6 | M1V | JOY1DAT Vertical Clock |
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| 7 | M1VQ | JOY1DAT Vertical Clock (quadrature) |
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+--------+----------+-----------------------------------------+
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Bits 1 and 0 of each counter (Y1-Y0,X1-X0) may be
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read to determine the state of the related input signal pair.
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This allows these pins to double as joystick switch inputs.
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Joystick switch closures can be deciphered as follows:
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+------------+------+---------------------------------+
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| Directions | Pin# | Counter bits |
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+------------+------+---------------------------------+
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| Forward | 1 | Y1 xor Y0 (BIT#09 xor BIT#08) |
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| Left | 3 | Y1 |
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| Back | 2 | X1 xor X0 (BIT#01 xor BIT#00) |
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| Right | 4 | X1 |
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+------------+------+---------------------------------+
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-------------------------------------------------------------------------------
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NAME rev ADDR type chip Description
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JOYTEST 036 W Denise Write to all 4 joystick-mouse counters at once.
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Mouse counter write test data:
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BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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JOYxDAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx
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JOYxDAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx
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-------------------------------------------------------------------------------
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NAME rev ADDR type chip Description
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POT0DAT h 012 R Paula Pot counter data left pair (vert, horiz)
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POT1DAT h 014 R Paula Pot counter data right pair (vert,horiz)
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These addresses each read a pair of 8 bit pot counters.
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(4 counters total). The bit assignment for both
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addresses is shown below. The counters are stopped by signals
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from 2 controller connectors (left-right) with 2 pins each.
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BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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RIGHT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
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LEFT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
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+--------------------------+-------+
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| CONNECTORS | PAULA |
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+-------+------+-----+-----+-------+
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| Loc. | Dir. | Sym | pin | pin |
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+-------+------+-----+-----+-------+
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| RIGHT | Y | RX | 9 | 33 |
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| RIGHT | X | RX | 5 | 32 |
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| LEFT | Y | LY | 9 | 36 |
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| LEFT | X | LX | 5 | 35 |
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+-------+------+-----+-----+-------+
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With normal (NTSC or PAL) horiz. line rate, the pots will
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give a full scale (FF) reading with about 500kohms in one
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frame time. With proportionally faster horiz line times,
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the counters will count proportionally faster.
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This should be noted when doing variable beam displays.
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-------------------------------------------------------------------------------
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NAME rev ADDR type chip Description
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POTGO 034 W Paula Pot port (4 bit) bi-direction and data, and pot counter start.
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-------------------------------------------------------------------------------
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NAME rev ADDR type chip Description
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POTINP 016 R Paula Pot pin data read
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This register controls a 4 bit bi-direction I/O port
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that shares the same 4 pins as the 4 pot counters above.
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+-------+----------+---------------------------------------------+
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| BIT# | FUNCTION | DESCRIPTION |
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+-------+----------+---------------------------------------------+
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| 15 | OUTRY | Output enable for Paula pin 33 |
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| 14 | DATRY | I/O data Paula pin 33 |
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| 13 | OUTRX | Output enable for Paula pin 32 |
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| 12 | DATRX | I/O data Paula pin 32 |
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| 11 | OUTLY | Out put enable for Paula pin 36 |
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| 10 | DATLY | I/O data Paula pin 36 |
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| 09 | OUTLX | Output enable for Paula pin 35 |
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| 08 | DATLX | I/O data Paula pin 35 |
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| 07-01 | X | Not used |
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| 00 | START | Start pots (dump capacitors,start counters) |
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+-------+----------+---------------------------------------------+
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-------------------------------------------------------------------------------
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