2fb6999dd0
Print the CXL Error Log field as found in CXL Protocol Error Section. The CXL RAS Capability structure will be reused by OS First Handling and the duplication/appropriate placement will be addressed eventually. Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
22 lines
468 B
C
22 lines
468 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2022 Advanced Micro Devices, Inc.
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*
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* Author: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
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*/
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#ifndef LINUX_CXL_ERR_H
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#define LINUX_CXL_ERR_H
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/* CXL RAS Capability Structure, CXL v3.1 sec 8.2.4.16 */
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struct cxl_ras_capability_regs {
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u32 uncor_status;
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u32 uncor_mask;
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u32 uncor_severity;
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u32 cor_status;
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u32 cor_mask;
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u32 cap_control;
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u32 header_log[16];
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};
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#endif //__CXL_ERR_
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