152 lines
3.6 KiB
C
152 lines
3.6 KiB
C
/*
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* Copyright 2002 Momentum Computer
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* Author: mdharm@momenco.com
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*
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* arch/mips/momentum/ocelot_c/cpci-irq.c
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* Interrupt routines for cpci. Interrupt numbers are assigned from
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* CPCI_IRQ_BASE to CPCI_IRQ_BASE+8 (8 interrupt sources).
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*
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* Note that the high-level software will need to be careful about using
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* these interrupts. If this board is asserting a cPCI interrupt, it will
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* also see the asserted interrupt. Care must be taken to avoid an
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* interrupt flood.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <asm/ptrace.h>
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <asm/io.h>
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#include "ocelot_c_fpga.h"
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#define CPCI_IRQ_BASE 8
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static inline int ls1bit8(unsigned int x)
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{
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int b = 7, s;
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s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
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s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
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s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
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return b;
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}
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/* mask off an interrupt -- 0 is enable, 1 is disable */
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static inline void mask_cpci_irq(unsigned int irq)
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{
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uint32_t value;
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value = OCELOT_FPGA_READ(INTMASK);
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value |= 1 << (irq - CPCI_IRQ_BASE);
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OCELOT_FPGA_WRITE(value, INTMASK);
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/* read the value back to assure that it's really been written */
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value = OCELOT_FPGA_READ(INTMASK);
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}
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/* unmask an interrupt -- 0 is enable, 1 is disable */
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static inline void unmask_cpci_irq(unsigned int irq)
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{
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uint32_t value;
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value = OCELOT_FPGA_READ(INTMASK);
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value &= ~(1 << (irq - CPCI_IRQ_BASE));
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OCELOT_FPGA_WRITE(value, INTMASK);
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/* read the value back to assure that it's really been written */
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value = OCELOT_FPGA_READ(INTMASK);
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}
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/*
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* Enables the IRQ in the FPGA
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*/
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static void enable_cpci_irq(unsigned int irq)
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{
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unmask_cpci_irq(irq);
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}
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/*
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* Initialize the IRQ in the FPGA
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*/
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static unsigned int startup_cpci_irq(unsigned int irq)
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{
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unmask_cpci_irq(irq);
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return 0;
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}
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/*
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* Disables the IRQ in the FPGA
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*/
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static void disable_cpci_irq(unsigned int irq)
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{
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mask_cpci_irq(irq);
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}
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/*
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* Masks and ACKs an IRQ
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*/
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static void mask_and_ack_cpci_irq(unsigned int irq)
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{
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mask_cpci_irq(irq);
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}
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/*
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* End IRQ processing
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*/
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static void end_cpci_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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unmask_cpci_irq(irq);
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}
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/*
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* Interrupt handler for interrupts coming from the FPGA chip.
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* It could be built in ethernet ports etc...
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*/
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void ll_cpci_irq(struct pt_regs *regs)
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{
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unsigned int irq_src, irq_mask;
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/* read the interrupt status registers */
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irq_src = OCELOT_FPGA_READ(INTSTAT);
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irq_mask = OCELOT_FPGA_READ(INTMASK);
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/* mask for just the interrupts we want */
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irq_src &= ~irq_mask;
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do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE, regs);
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}
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#define shutdown_cpci_irq disable_cpci_irq
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struct hw_interrupt_type cpci_irq_type = {
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.typename = "CPCI/FPGA",
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.startup = startup_cpci_irq,
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.shutdown = shutdown_cpci_irq,
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.enable = enable_cpci_irq,
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.disable = disable_cpci_irq,
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.ack = mask_and_ack_cpci_irq,
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.end = end_cpci_irq,
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};
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void cpci_irq_init(void)
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{
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int i;
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/* Reset irq handlers pointers to NULL */
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for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 2;
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irq_desc[i].handler = &cpci_irq_type;
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}
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}
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