1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
160 lines
5.2 KiB
C
160 lines
5.2 KiB
C
/***********************************************************************
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* arch/mips/ddb5xxx/ddb5477/debug.c
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* vrc5477 specific debug routines.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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***********************************************************************
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*/
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#include <linux/kernel.h>
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#include <asm/mipsregs.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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typedef struct {
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const char *regname;
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unsigned regaddr;
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} Register;
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void jsun_show_regs(char *name, Register *regs)
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{
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int i;
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printk("\nshow regs: %s\n", name);
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for(i=0;regs[i].regname!= NULL; i++) {
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printk("%-16s= %08x\t\t(@%08x)\n",
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regs[i].regname,
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*(unsigned *)(regs[i].regaddr),
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regs[i].regaddr);
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}
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}
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static Register int_regs[] = {
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{"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0},
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{"DDB_INTCTRL1", DDB_BASE + DDB_INTCTRL1},
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{"DDB_INTCTRL2", DDB_BASE + DDB_INTCTRL2},
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{"DDB_INTCTRL3", DDB_BASE + DDB_INTCTRL3},
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{"DDB_INT0STAT", DDB_BASE + DDB_INT0STAT},
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{"DDB_INT1STAT", DDB_BASE + DDB_INT1STAT},
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{"DDB_INT2STAT", DDB_BASE + DDB_INT2STAT},
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{"DDB_INT3STAT", DDB_BASE + DDB_INT3STAT},
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{"DDB_INT4STAT", DDB_BASE + DDB_INT4STAT},
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{"DDB_NMISTAT", DDB_BASE + DDB_NMISTAT},
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{"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0},
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{"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1},
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{NULL, 0x0}
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};
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void vrc5477_show_int_regs()
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{
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jsun_show_regs("interrupt registers", int_regs);
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printk("CPU CAUSE = %08x\n", read_c0_cause());
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printk("CPU STATUS = %08x\n", read_c0_status());
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}
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static Register pdar_regs[] = {
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{"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0},
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{"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1},
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{"DDB_LCS0", DDB_BASE + DDB_LCS0},
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{"DDB_LCS1", DDB_BASE + DDB_LCS1},
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{"DDB_LCS2", DDB_BASE + DDB_LCS2},
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{"DDB_INTCS", DDB_BASE + DDB_INTCS},
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{"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS},
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{"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
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{"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
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{"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
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{"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
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{NULL, 0x0}
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};
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void vrc5477_show_pdar_regs(void)
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{
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jsun_show_regs("PDAR regs", pdar_regs);
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}
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static Register bar_regs[] = {
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{"DDB_BARC0", DDB_BASE + DDB_BARC0},
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{"DDB_BARM010", DDB_BASE + DDB_BARM010},
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{"DDB_BARM230", DDB_BASE + DDB_BARM230},
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{"DDB_BAR00", DDB_BASE + DDB_BAR00},
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{"DDB_BAR10", DDB_BASE + DDB_BAR10},
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{"DDB_BAR20", DDB_BASE + DDB_BAR20},
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{"DDB_BAR30", DDB_BASE + DDB_BAR30},
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{"DDB_BAR40", DDB_BASE + DDB_BAR40},
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{"DDB_BAR50", DDB_BASE + DDB_BAR50},
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{"DDB_BARB0", DDB_BASE + DDB_BARB0},
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{"DDB_BARC1", DDB_BASE + DDB_BARC1},
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{"DDB_BARM011", DDB_BASE + DDB_BARM011},
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{"DDB_BARM231", DDB_BASE + DDB_BARM231},
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{"DDB_BAR01", DDB_BASE + DDB_BAR01},
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{"DDB_BAR11", DDB_BASE + DDB_BAR11},
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{"DDB_BAR21", DDB_BASE + DDB_BAR21},
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{"DDB_BAR31", DDB_BASE + DDB_BAR31},
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{"DDB_BAR41", DDB_BASE + DDB_BAR41},
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{"DDB_BAR51", DDB_BASE + DDB_BAR51},
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{"DDB_BARB1", DDB_BASE + DDB_BARB1},
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{NULL, 0x0}
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};
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void vrc5477_show_bar_regs(void)
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{
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jsun_show_regs("BAR regs", bar_regs);
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}
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static Register pci_regs[] = {
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{"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
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{"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
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{"DDB_PCIINIT00", DDB_BASE + DDB_PCIINIT00},
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{"DDB_PCIINIT10", DDB_BASE + DDB_PCIINIT10},
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{"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L},
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{"DDB_PCICTL0_H", DDB_BASE + DDB_PCICTL0_H},
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{"DDB_PCIARB0_L", DDB_BASE + DDB_PCIARB0_L},
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{"DDB_PCIARB0_H", DDB_BASE + DDB_PCIARB0_H},
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{"DDB_PCISWP0", DDB_BASE + DDB_PCISWP0},
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{"DDB_PCIERR0", DDB_BASE + DDB_PCIERR0},
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{"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
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{"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
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{"DDB_PCIINIT01", DDB_BASE + DDB_PCIINIT01},
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{"DDB_PCIINIT11", DDB_BASE + DDB_PCIINIT11},
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{"DDB_PCICTL1_L", DDB_BASE + DDB_PCICTL1_L},
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{"DDB_PCICTL1_H", DDB_BASE + DDB_PCICTL1_H},
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{"DDB_PCIARB1_L", DDB_BASE + DDB_PCIARB1_L},
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{"DDB_PCIARB1_H", DDB_BASE + DDB_PCIARB1_H},
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{"DDB_PCISWP1", DDB_BASE + DDB_PCISWP1},
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{"DDB_PCIERR1", DDB_BASE + DDB_PCIERR1},
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{NULL, 0x0}
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};
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void vrc5477_show_pci_regs(void)
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{
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jsun_show_regs("PCI regs", pci_regs);
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}
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static Register lb_regs[] = {
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{"DDB_LCNFG", DDB_BASE + DDB_LCNFG},
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{"DDB_LCST0", DDB_BASE + DDB_LCST0},
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{"DDB_LCST1", DDB_BASE + DDB_LCST1},
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{"DDB_LCST2", DDB_BASE + DDB_LCST2},
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{"DDB_ERRADR", DDB_BASE + DDB_ERRADR},
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{"DDB_ERRCS", DDB_BASE + DDB_ERRCS},
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{"DDB_BTM", DDB_BASE + DDB_BTM},
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{"DDB_BCST", DDB_BASE + DDB_BCST},
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{NULL, 0x0}
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};
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void vrc5477_show_lb_regs(void)
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{
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jsun_show_regs("Local Bus regs", lb_regs);
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}
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void vrc5477_show_all_regs(void)
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{
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vrc5477_show_pdar_regs();
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vrc5477_show_pci_regs();
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vrc5477_show_bar_regs();
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vrc5477_show_int_regs();
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vrc5477_show_lb_regs();
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}
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