1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
352 lines
7.4 KiB
C
352 lines
7.4 KiB
C
/*
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* arch/ppc/platforms/pcore_setup.c
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*
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* Setup routines for Force PCORE boards
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*
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* Author: Matt Porter <mporter@mvista.com>
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*
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* 2001 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/types.h>
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#include <linux/major.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/time.h>
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#include <asm/i8259.h>
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#include <asm/mpc10x.h>
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#include <asm/todc.h>
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#include <asm/bootinfo.h>
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#include <asm/kgdb.h>
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#include "pcore.h"
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extern unsigned long loops_per_jiffy;
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static int board_type;
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static inline int __init
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pcore_6750_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{9, 10, 11, 12}, /* IDSEL 24 - DEC 21554 */
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{10, 0, 0, 0}, /* IDSEL 25 - DEC 21143 */
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{11, 12, 9, 10}, /* IDSEL 26 - PMC I */
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{12, 9, 10, 11}, /* IDSEL 27 - PMC II */
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{0, 0, 0, 0}, /* IDSEL 28 - unused */
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{0, 0, 9, 0}, /* IDSEL 29 - unused */
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{0, 0, 0, 0}, /* IDSEL 30 - Winbond */
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};
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const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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};
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static inline int __init
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pcore_680_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{9, 10, 11, 12}, /* IDSEL 24 - Sentinel */
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{10, 0, 0, 0}, /* IDSEL 25 - i82559 #1 */
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{11, 12, 9, 10}, /* IDSEL 26 - PMC I */
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{12, 9, 10, 11}, /* IDSEL 27 - PMC II */
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{9, 0, 0, 0}, /* IDSEL 28 - i82559 #2 */
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{0, 0, 0, 0}, /* IDSEL 29 - unused */
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{0, 0, 0, 0}, /* IDSEL 30 - Winbond */
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};
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const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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};
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void __init
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pcore_pcibios_fixup(void)
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{
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struct pci_dev *dev;
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if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
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PCI_DEVICE_ID_WINBOND_83C553,
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0)))
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{
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/* Reroute interrupts both IDE channels to 15 */
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pci_write_config_byte(dev,
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PCORE_WINBOND_IDE_INT,
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0xff);
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/* Route INTA-D to IRQ9-12, respectively */
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pci_write_config_word(dev,
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PCORE_WINBOND_PCI_INT,
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0x9abc);
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/*
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* Set up 8259 edge/level triggering
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*/
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outb(0x00, PCORE_WINBOND_PRI_EDG_LVL);
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outb(0x1e, PCORE_WINBOND_SEC_EDG_LVL);
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pci_dev_put(dev);
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}
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}
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int __init
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pcore_find_bridges(void)
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{
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struct pci_controller* hose;
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int host_bridge, board_type;
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hose = pcibios_alloc_controller();
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if (!hose)
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return 0;
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mpc10x_bridge_init(hose,
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MPC10X_MEM_MAP_B,
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MPC10X_MEM_MAP_B,
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MPC10X_MAPB_EUMB_BASE);
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/* Determine board type */
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early_read_config_dword(hose,
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0,
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PCI_DEVFN(0,0),
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PCI_VENDOR_ID,
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&host_bridge);
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if (host_bridge == MPC10X_BRIDGE_106)
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board_type = PCORE_TYPE_6750;
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else /* MPC10X_BRIDGE_107 */
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board_type = PCORE_TYPE_680;
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hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
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ppc_md.pcibios_fixup = pcore_pcibios_fixup;
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ppc_md.pci_swizzle = common_swizzle;
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if (board_type == PCORE_TYPE_6750)
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ppc_md.pci_map_irq = pcore_6750_map_irq;
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else /* PCORE_TYPE_680 */
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ppc_md.pci_map_irq = pcore_680_map_irq;
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return board_type;
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}
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/* Dummy variable to satisfy mpc10x_common.o */
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void *OpenPIC_Addr;
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static int
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pcore_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: Force Computers\n");
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if (board_type == PCORE_TYPE_6750)
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seq_printf(m, "machine\t\t: PowerCore 6750\n");
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else /* PCORE_TYPE_680 */
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seq_printf(m, "machine\t\t: PowerCore 680\n");
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seq_printf(m, "L2\t\t: " );
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if (board_type == PCORE_TYPE_6750)
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switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
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{
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case PCORE_DCCR_L2_0KB:
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seq_printf(m, "nocache");
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break;
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case PCORE_DCCR_L2_256KB:
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seq_printf(m, "256KB");
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break;
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case PCORE_DCCR_L2_1MB:
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seq_printf(m, "1MB");
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break;
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case PCORE_DCCR_L2_512KB:
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seq_printf(m, "512KB");
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break;
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default:
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seq_printf(m, "error");
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break;
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}
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else /* PCORE_TYPE_680 */
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switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
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{
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case PCORE_DCCR_L2_2MB:
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seq_printf(m, "2MB");
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break;
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case PCORE_DCCR_L2_256KB:
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seq_printf(m, "reserved");
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break;
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case PCORE_DCCR_L2_1MB:
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seq_printf(m, "1MB");
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break;
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case PCORE_DCCR_L2_512KB:
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seq_printf(m, "512KB");
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break;
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default:
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seq_printf(m, "error");
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break;
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}
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seq_printf(m, "\n");
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return 0;
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}
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static void __init
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pcore_setup_arch(void)
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{
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000/HZ;
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/* Lookup PCI host bridges */
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board_type = pcore_find_bridges();
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_SDA2;
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#endif
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printk(KERN_INFO "Force PowerCore ");
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if (board_type == PCORE_TYPE_6750)
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printk("6750\n");
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else
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printk("680\n");
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printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
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_set_L2CR(L2CR_L2E | _get_L2CR());
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}
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static void
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pcore_restart(char *cmd)
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{
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local_irq_disable();
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/* Hard reset */
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writeb(0x11, 0xfe000332);
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while(1);
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}
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static void
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pcore_halt(void)
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{
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local_irq_disable();
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/* Turn off user LEDs */
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writeb(0x00, 0xfe000300);
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while (1);
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}
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static void
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pcore_power_off(void)
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{
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pcore_halt();
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}
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static void __init
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pcore_init_IRQ(void)
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{
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int i;
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for ( i = 0 ; i < 16 ; i++ )
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irq_desc[i].handler = &i8259_pic;
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i8259_init(0);
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}
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/*
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* Set BAT 3 to map 0xf0000000 to end of physical memory space.
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*/
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static __inline__ void
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pcore_set_bat(void)
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{
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mb();
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mtspr(SPRN_DBAT3U, 0xf0001ffe);
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mtspr(SPRN_DBAT3L, 0xfe80002a);
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mb();
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}
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static unsigned long __init
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pcore_find_end_of_memory(void)
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{
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return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
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}
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static void __init
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pcore_map_io(void)
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{
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io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
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}
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TODC_ALLOC();
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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parse_bootinfo(find_bootinfo());
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/* Cover I/O space with a BAT */
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/* yuck, better hope your ram size is a power of 2 -- paulus */
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pcore_set_bat();
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isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
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isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
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pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
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ppc_md.setup_arch = pcore_setup_arch;
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ppc_md.show_cpuinfo = pcore_show_cpuinfo;
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ppc_md.init_IRQ = pcore_init_IRQ;
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ppc_md.get_irq = i8259_irq;
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ppc_md.find_end_of_memory = pcore_find_end_of_memory;
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ppc_md.setup_io_mappings = pcore_map_io;
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ppc_md.restart = pcore_restart;
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ppc_md.power_off = pcore_power_off;
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ppc_md.halt = pcore_halt;
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TODC_INIT(TODC_TYPE_MK48T59,
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PCORE_NVRAM_AS0,
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PCORE_NVRAM_AS1,
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PCORE_NVRAM_DATA,
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8);
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ppc_md.time_init = todc_time_init;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.calibrate_decr = todc_calibrate_decr;
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ppc_md.nvram_read_val = todc_m48txx_read_val;
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ppc_md.nvram_write_val = todc_m48txx_write_val;
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#ifdef CONFIG_SERIAL_TEXT_DEBUG
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ppc_md.progress = gen550_progress;
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#endif
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#ifdef CONFIG_KGDB
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ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
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#endif
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}
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