a6dbba77a9
This patch adds on-chip PCI bridge support for the PQ2 family. The incomplete existent code is updated with interrupt handling stuff and board-specific bits for 8272ADS and PQ2FADS; the related files were renamed (from m8260_pci to m82xx_pci) to be of more generic fashion. This is tested with 8266ADS and 8272ADS, should work on PQ2FADS as well. Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
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#ifndef _PPC_KERNEL_M82XX_PCI_H
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#define _PPC_KERNEL_M82XX_PCI_H
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#include <asm/m8260_pci.h>
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/*
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* Local->PCI map (from CPU) controlled by
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* MPC826x master window
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*
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* 0xF6000000 - 0xF7FFFFFF IO space
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* 0x80000000 - 0xBFFFFFFF CPU2PCI memory space PCIBR0
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*
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* 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
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* 0xA0000000 - 0xBFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
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* 0xF6000000 - 0xF7FFFFFF 32-bit PCI IO (Outbound ATU #3)
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*
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* PCI->Local map (from PCI)
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* MPC826x slave window controlled by
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*
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* 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
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*/
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/*
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* Slave window that allows PCI masters to access MPC826x local memory.
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* This window is set up using the first set of Inbound ATU registers
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*/
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#ifndef M82xx_PCI_SLAVE_MEM_LOCAL
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#define M82xx_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart)
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#define M82xx_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart)
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#define M82xx_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize)
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#endif
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/*
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* This is the window that allows the CPU to access PCI address space.
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* It will be setup with the SIU PCIBR0 register. All three PCI master
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* windows, which allow the CPU to access PCI prefetch, non prefetch,
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* and IO space (see below), must all fit within this window.
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*/
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#ifndef M82xx_PCI_LOWER_MEM
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#define M82xx_PCI_LOWER_MEM 0x80000000
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#define M82xx_PCI_UPPER_MEM 0x9fffffff
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#define M82xx_PCI_MEM_OFFSET 0x00000000
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#define M82xx_PCI_MEM_SIZE 0x20000000
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#endif
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#ifndef M82xx_PCI_LOWER_MMIO
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#define M82xx_PCI_LOWER_MMIO 0xa0000000
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#define M82xx_PCI_UPPER_MMIO 0xafffffff
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#define M82xx_PCI_MMIO_OFFSET 0x00000000
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#define M82xx_PCI_MMIO_SIZE 0x20000000
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#endif
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#ifndef M82xx_PCI_LOWER_IO
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#define M82xx_PCI_LOWER_IO 0x00000000
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#define M82xx_PCI_UPPER_IO 0x01ffffff
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#define M82xx_PCI_IO_BASE 0xf6000000
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#define M82xx_PCI_IO_SIZE 0x02000000
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#endif
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#ifndef M82xx_PCI_PRIM_WND_SIZE
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#define M82xx_PCI_PRIM_WND_SIZE ~(M82xx_PCI_IO_SIZE - 1U)
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#define M82xx_PCI_PRIM_WND_BASE (M82xx_PCI_IO_BASE)
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#endif
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#ifndef M82xx_PCI_SEC_WND_SIZE
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#define M82xx_PCI_SEC_WND_SIZE ~(M82xx_PCI_MEM_SIZE + M82xx_PCI_MMIO_SIZE - 1U)
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#define M82xx_PCI_SEC_WND_BASE (M82xx_PCI_LOWER_MEM)
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#endif
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#ifndef POTA_ADDR_SHIFT
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#define POTA_ADDR_SHIFT 12
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#endif
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#ifndef PITA_ADDR_SHIFT
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#define PITA_ADDR_SHIFT 12
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#endif
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#ifndef _IO_BASE
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#define _IO_BASE isa_io_base
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#endif
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#ifdef CONFIG_8260_PCI9
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struct pci_controller;
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extern void setup_m8260_indirect_pci(struct pci_controller* hose,
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u32 cfg_addr, u32 cfg_data);
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#else
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#define setup_m8260_indirect_pci setup_indirect_pci
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#endif
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#endif /* _PPC_KERNEL_M8260_PCI_H */
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