4bedea9454
The attached patches provides part 2 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
37 lines
565 B
ArmAsm
37 lines
565 B
ArmAsm
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#include <xtensa/config/specreg.h>
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#include <xtensa/config/core.h>
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#include <linux/config.h>
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#include <asm/bootparam.h>
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/* ResetVector
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*/
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.section .ResetVector.text, "ax"
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.global _ResetVector
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_ResetVector:
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_j reset
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.align 4
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RomInitAddr:
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.word 0xd0001000
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RomBootParam:
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.word _bootparam
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reset:
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l32r a0, RomInitAddr
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l32r a2, RomBootParam
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movi a3, 0
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movi a4, 0
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jx a0
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.align 4
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.section .bootstrap.data, "aw"
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.globl _bootparam
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_bootparam:
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.short BP_TAG_FIRST
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.short 4
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.long BP_VERSION
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.short BP_TAG_LAST
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.short 0
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.long 0
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