drivers: iio: imu: Add support for adis1657x family
Add support for ADIS1657X family devices in already exiting ADIS16475 driver. Signed-off-by: Ramona Gradinariu <ramona.bolboaca13@gmail.com> Link: https://lore.kernel.org/r/20240527142618.275897-10-ramona.bolboaca13@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Ramona Gradinariu
Jonathan Cameron
parent
647a2c81fe
commit
f95920baa0
1 changed files with 561 additions and 51 deletions
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@ -14,6 +14,7 @@
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/imu/adis.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/irq.h>
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#include <linux/lcm.h>
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@ -52,6 +53,8 @@
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FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x)
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#define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2)
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#define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x)
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#define ADIS16575_SYNC_4KHZ_MASK BIT(11)
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#define ADIS16575_SYNC_4KHZ(x) FIELD_PREP(ADIS16575_SYNC_4KHZ_MASK, x)
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#define ADIS16475_REG_UP_SCALE 0x62
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#define ADIS16475_REG_DEC_RATE 0x64
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#define ADIS16475_REG_GLOB_CMD 0x68
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@ -66,14 +69,31 @@
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#define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x)
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/* number of data elements in burst mode */
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#define ADIS16475_BURST32_MAX_DATA_NO_TS32 32
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#define ADIS16575_BURST32_DATA_TS32 34
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#define ADIS16475_BURST_MAX_DATA 20
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#define ADIS16475_MAX_SCAN_DATA 20
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/* spi max speed in brust mode */
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#define ADIS16475_BURST_MAX_SPEED 1000000
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#define ADIS16575_BURST_MAX_SPEED 8000000
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#define ADIS16475_LSB_DEC_MASK 0
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#define ADIS16475_LSB_FIR_MASK 1
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#define ADIS16500_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0)
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#define ADIS16500_BURST_DATA_SEL_1_CHN_MASK GENMASK(12, 7)
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#define ADIS16575_MAX_FIFO_WM 511UL
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#define ADIS16475_REG_FIFO_CTRL 0x5A
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#define ADIS16575_WM_LVL_MASK GENMASK(15, 4)
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#define ADIS16575_WM_LVL(x) FIELD_PREP(ADIS16575_WM_LVL_MASK, x)
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#define ADIS16575_WM_POL_MASK BIT(3)
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#define ADIS16575_WM_POL(x) FIELD_PREP(ADIS16575_WM_POL_MASK, x)
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#define ADIS16575_WM_EN_MASK BIT(2)
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#define ADIS16575_WM_EN(x) FIELD_PREP(ADIS16575_WM_EN_MASK, x)
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#define ADIS16575_OVERFLOW_MASK BIT(1)
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#define ADIS16575_STOP_ENQUEUE FIELD_PREP(ADIS16575_OVERFLOW_MASK, 0)
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#define ADIS16575_OVERWRITE_OLDEST FIELD_PREP(ADIS16575_OVERFLOW_MASK, 1)
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#define ADIS16575_FIFO_EN_MASK BIT(0)
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#define ADIS16575_FIFO_EN(x) FIELD_PREP(ADIS16575_FIFO_EN_MASK, x)
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#define ADIS16575_FIFO_FLUSH_CMD BIT(5)
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#define ADIS16575_REG_FIFO_CNT 0x3C
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enum {
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ADIS16475_SYNC_DIRECT = 1,
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@ -95,6 +115,8 @@ struct adis16475_chip_info {
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const char *name;
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#define ADIS16475_HAS_BURST32 BIT(0)
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#define ADIS16475_HAS_BURST_DELTA_DATA BIT(1)
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#define ADIS16475_HAS_TIMESTAMP32 BIT(2)
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#define ADIS16475_NEEDS_BURST_REQUEST BIT(3)
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const long flags;
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u32 num_channels;
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u32 gyro_max_val;
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@ -116,6 +138,7 @@ struct adis16475 {
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bool burst32;
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unsigned long lsb_flag;
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u16 sync_mode;
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u16 fifo_watermark;
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/* Alignment needed for the timestamp */
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__be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8);
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};
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@ -442,6 +465,124 @@ static int adis16475_set_filter(struct adis16475 *st, const u32 filter)
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return 0;
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}
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static ssize_t adis16475_get_fifo_enabled(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct adis16475 *st = iio_priv(indio_dev);
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int ret;
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u16 val;
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ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val);
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if (ret)
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return ret;
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return sysfs_emit(buf, "%lu\n", FIELD_GET(ADIS16575_FIFO_EN_MASK, val));
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}
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static ssize_t adis16475_get_fifo_watermark(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct adis16475 *st = iio_priv(indio_dev);
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int ret;
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u16 val;
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ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val);
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if (ret)
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return ret;
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return sysfs_emit(buf, "%lu\n", FIELD_GET(ADIS16575_WM_LVL_MASK, val) + 1);
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}
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static ssize_t hwfifo_watermark_min_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return sysfs_emit(buf, "1\n");
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}
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static ssize_t hwfifo_watermark_max_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return sysfs_emit(buf, "%lu\n", ADIS16575_MAX_FIFO_WM);
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}
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static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
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static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
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static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
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adis16475_get_fifo_watermark, NULL, 0);
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static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
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adis16475_get_fifo_enabled, NULL, 0);
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static const struct iio_dev_attr *adis16475_fifo_attributes[] = {
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&iio_dev_attr_hwfifo_watermark_min,
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&iio_dev_attr_hwfifo_watermark_max,
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&iio_dev_attr_hwfifo_watermark,
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&iio_dev_attr_hwfifo_enabled,
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NULL
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};
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static int adis16475_buffer_postenable(struct iio_dev *indio_dev)
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{
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struct adis16475 *st = iio_priv(indio_dev);
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struct adis *adis = &st->adis;
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return adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL,
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ADIS16575_FIFO_EN_MASK, (u16)ADIS16575_FIFO_EN(1));
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}
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static int adis16475_buffer_postdisable(struct iio_dev *indio_dev)
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{
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struct adis16475 *st = iio_priv(indio_dev);
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struct adis *adis = &st->adis;
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int ret;
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adis_dev_lock(&st->adis);
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ret = __adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL,
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ADIS16575_FIFO_EN_MASK, (u16)ADIS16575_FIFO_EN(0));
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if (ret)
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goto unlock;
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ret = __adis_write_reg_16(adis, ADIS16475_REG_GLOB_CMD,
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ADIS16575_FIFO_FLUSH_CMD);
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unlock:
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adis_dev_unlock(&st->adis);
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return ret;
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}
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static const struct iio_buffer_setup_ops adis16475_buffer_ops = {
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.postenable = adis16475_buffer_postenable,
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.postdisable = adis16475_buffer_postdisable,
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};
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static int adis16475_set_watermark(struct iio_dev *indio_dev, unsigned int val)
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{
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struct adis16475 *st = iio_priv(indio_dev);
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int ret;
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u16 wm_lvl;
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adis_dev_lock(&st->adis);
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val = min_t(unsigned int, val, ADIS16575_MAX_FIFO_WM);
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wm_lvl = ADIS16575_WM_LVL(val - 1);
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ret = __adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, ADIS16575_WM_LVL_MASK, wm_lvl);
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if (ret)
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goto unlock;
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st->fifo_watermark = val;
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unlock:
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adis_dev_unlock(&st->adis);
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return ret;
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}
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static const u32 adis16475_calib_regs[] = {
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[ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L,
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[ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L,
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@ -651,6 +792,22 @@ static const struct iio_chan_spec adis16475_channels[] = {
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IIO_CHAN_SOFT_TIMESTAMP(7)
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};
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static const struct iio_chan_spec adis16575_channels[] = {
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ADIS16475_GYRO_CHANNEL(X),
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ADIS16475_GYRO_CHANNEL(Y),
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ADIS16475_GYRO_CHANNEL(Z),
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ADIS16475_ACCEL_CHANNEL(X),
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ADIS16475_ACCEL_CHANNEL(Y),
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ADIS16475_ACCEL_CHANNEL(Z),
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ADIS16475_TEMP_CHANNEL(),
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ADIS16475_DELTANG_CHAN(X),
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ADIS16475_DELTANG_CHAN(Y),
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ADIS16475_DELTANG_CHAN(Z),
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ADIS16475_DELTVEL_CHAN(X),
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ADIS16475_DELTVEL_CHAN(Y),
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ADIS16475_DELTVEL_CHAN(Z),
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};
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enum adis16475_variant {
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ADIS16470,
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ADIS16475_1,
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@ -673,6 +830,12 @@ enum adis16475_variant {
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ADIS16507_1,
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ADIS16507_2,
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ADIS16507_3,
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ADIS16575_2,
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ADIS16575_3,
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ADIS16576_2,
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ADIS16576_3,
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ADIS16577_2,
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ADIS16577_3,
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};
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enum {
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@ -731,6 +894,12 @@ static const struct adis16475_sync adis16475_sync_mode[] = {
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{ ADIS16475_SYNC_PULSE, 1000, 2100 },
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};
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static const struct adis16475_sync adis16575_sync_mode[] = {
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{ ADIS16475_SYNC_OUTPUT },
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{ ADIS16475_SYNC_DIRECT, 1900, 4100 },
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{ ADIS16475_SYNC_SCALED, 1, 400 },
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};
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static const struct adis_timeout adis16475_timeouts = {
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.reset_ms = 200,
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.sw_reset_ms = 200,
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@ -1162,6 +1331,144 @@ static const struct adis16475_chip_info adis16475_chip_info[] = {
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ADIS16475_BURST32_MAX_DATA_NO_TS32,
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ADIS16475_BURST_MAX_SPEED, false),
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},
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[ADIS16575_2] = {
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.name = "adis16575-2",
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.num_channels = ARRAY_SIZE(adis16575_channels),
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.channels = adis16575_channels,
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.gyro_max_val = 1,
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.gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
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.accel_max_val = 8,
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.accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
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.temp_scale = 100,
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.deltang_max_val = IIO_DEGREE_TO_RAD(450),
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.deltvel_max_val = 100,
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.int_clk = 4000,
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.max_dec = 3999,
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.sync = adis16575_sync_mode,
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.num_sync = ARRAY_SIZE(adis16575_sync_mode),
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.flags = ADIS16475_HAS_BURST32 |
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ADIS16475_HAS_BURST_DELTA_DATA |
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ADIS16475_NEEDS_BURST_REQUEST |
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ADIS16475_HAS_TIMESTAMP32,
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.adis_data = ADIS16475_DATA(16575, &adis16475_timeouts,
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ADIS16575_BURST32_DATA_TS32,
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ADIS16575_BURST_MAX_SPEED, true),
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},
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[ADIS16575_3] = {
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.name = "adis16575-3",
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.num_channels = ARRAY_SIZE(adis16575_channels),
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.channels = adis16575_channels,
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.gyro_max_val = 1,
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.gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
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.accel_max_val = 8,
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.accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
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.temp_scale = 100,
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.deltang_max_val = IIO_DEGREE_TO_RAD(2000),
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.deltvel_max_val = 100,
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.int_clk = 4000,
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.max_dec = 3999,
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.sync = adis16575_sync_mode,
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.num_sync = ARRAY_SIZE(adis16575_sync_mode),
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.flags = ADIS16475_HAS_BURST32 |
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ADIS16475_HAS_BURST_DELTA_DATA |
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ADIS16475_NEEDS_BURST_REQUEST |
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ADIS16475_HAS_TIMESTAMP32,
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.adis_data = ADIS16475_DATA(16575, &adis16475_timeouts,
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ADIS16575_BURST32_DATA_TS32,
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ADIS16575_BURST_MAX_SPEED, true),
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},
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[ADIS16576_2] = {
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.name = "adis16576-2",
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.num_channels = ARRAY_SIZE(adis16575_channels),
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.channels = adis16575_channels,
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.gyro_max_val = 1,
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.gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
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.accel_max_val = 40,
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.accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
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.temp_scale = 100,
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.deltang_max_val = IIO_DEGREE_TO_RAD(450),
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.deltvel_max_val = 125,
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.int_clk = 4000,
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.max_dec = 3999,
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.sync = adis16575_sync_mode,
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.num_sync = ARRAY_SIZE(adis16575_sync_mode),
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.flags = ADIS16475_HAS_BURST32 |
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ADIS16475_HAS_BURST_DELTA_DATA |
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ADIS16475_NEEDS_BURST_REQUEST |
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ADIS16475_HAS_TIMESTAMP32,
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.adis_data = ADIS16475_DATA(16576, &adis16475_timeouts,
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ADIS16575_BURST32_DATA_TS32,
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ADIS16575_BURST_MAX_SPEED, true),
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},
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[ADIS16576_3] = {
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.name = "adis16576-3",
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.num_channels = ARRAY_SIZE(adis16575_channels),
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.channels = adis16575_channels,
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.gyro_max_val = 1,
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.gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
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.accel_max_val = 40,
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.accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
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.temp_scale = 100,
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.deltang_max_val = IIO_DEGREE_TO_RAD(2000),
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.deltvel_max_val = 125,
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.int_clk = 4000,
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.max_dec = 3999,
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.sync = adis16575_sync_mode,
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.num_sync = ARRAY_SIZE(adis16575_sync_mode),
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.flags = ADIS16475_HAS_BURST32 |
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ADIS16475_HAS_BURST_DELTA_DATA |
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ADIS16475_NEEDS_BURST_REQUEST |
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ADIS16475_HAS_TIMESTAMP32,
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.adis_data = ADIS16475_DATA(16576, &adis16475_timeouts,
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ADIS16575_BURST32_DATA_TS32,
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ADIS16575_BURST_MAX_SPEED, true),
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},
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[ADIS16577_2] = {
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.name = "adis16577-2",
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.num_channels = ARRAY_SIZE(adis16575_channels),
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.channels = adis16575_channels,
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.gyro_max_val = 1,
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.gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
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.accel_max_val = 40,
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.accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
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.temp_scale = 100,
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.deltang_max_val = IIO_DEGREE_TO_RAD(450),
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.deltvel_max_val = 400,
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.int_clk = 4000,
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.max_dec = 3999,
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.sync = adis16575_sync_mode,
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.num_sync = ARRAY_SIZE(adis16575_sync_mode),
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.flags = ADIS16475_HAS_BURST32 |
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ADIS16475_HAS_BURST_DELTA_DATA |
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ADIS16475_NEEDS_BURST_REQUEST |
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ADIS16475_HAS_TIMESTAMP32,
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.adis_data = ADIS16475_DATA(16577, &adis16475_timeouts,
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ADIS16575_BURST32_DATA_TS32,
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ADIS16575_BURST_MAX_SPEED, true),
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},
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[ADIS16577_3] = {
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.name = "adis16577-3",
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.num_channels = ARRAY_SIZE(adis16575_channels),
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.channels = adis16575_channels,
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.gyro_max_val = 1,
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.gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
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.accel_max_val = 40,
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.accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
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.temp_scale = 100,
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.deltang_max_val = IIO_DEGREE_TO_RAD(2000),
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.deltvel_max_val = 400,
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.int_clk = 4000,
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.max_dec = 3999,
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.sync = adis16575_sync_mode,
|
||||
.num_sync = ARRAY_SIZE(adis16575_sync_mode),
|
||||
.flags = ADIS16475_HAS_BURST32 |
|
||||
ADIS16475_HAS_BURST_DELTA_DATA |
|
||||
ADIS16475_NEEDS_BURST_REQUEST |
|
||||
ADIS16475_HAS_TIMESTAMP32,
|
||||
.adis_data = ADIS16475_DATA(16577, &adis16475_timeouts,
|
||||
ADIS16575_BURST32_DATA_TS32,
|
||||
ADIS16575_BURST_MAX_SPEED, true),
|
||||
},
|
||||
};
|
||||
|
||||
static int adis16475_update_scan_mode(struct iio_dev *indio_dev,
|
||||
|
|
@ -1196,15 +1503,20 @@ static const struct iio_info adis16475_info = {
|
|||
.debugfs_reg_access = adis_debugfs_reg_access,
|
||||
};
|
||||
|
||||
static const struct iio_info adis16575_info = {
|
||||
.read_raw = &adis16475_read_raw,
|
||||
.write_raw = &adis16475_write_raw,
|
||||
.update_scan_mode = adis16475_update_scan_mode,
|
||||
.debugfs_reg_access = adis_debugfs_reg_access,
|
||||
.hwfifo_set_watermark = adis16475_set_watermark,
|
||||
};
|
||||
|
||||
static bool adis16475_validate_crc(const u8 *buffer, u16 crc,
|
||||
const bool burst32)
|
||||
u16 burst_size, u16 start_idx)
|
||||
{
|
||||
int i;
|
||||
/* extra 6 elements for low gyro and accel */
|
||||
const u16 sz = burst32 ? ADIS16475_BURST32_MAX_DATA_NO_TS32 :
|
||||
ADIS16475_BURST_MAX_DATA;
|
||||
|
||||
for (i = 0; i < sz - 2; i++)
|
||||
for (i = start_idx; i < burst_size - 2; i++)
|
||||
crc -= buffer[i];
|
||||
|
||||
return crc == 0;
|
||||
|
|
@ -1214,10 +1526,14 @@ static void adis16475_burst32_check(struct adis16475 *st)
|
|||
{
|
||||
int ret;
|
||||
struct adis *adis = &st->adis;
|
||||
u8 timestamp32 = 0;
|
||||
|
||||
if (!(st->info->flags & ADIS16475_HAS_BURST32))
|
||||
return;
|
||||
|
||||
if (st->info->flags & ADIS16475_HAS_TIMESTAMP32)
|
||||
timestamp32 = 1;
|
||||
|
||||
if (st->lsb_flag && !st->burst32) {
|
||||
const u16 en = ADIS16500_BURST32(1);
|
||||
|
||||
|
|
@ -1231,9 +1547,12 @@ static void adis16475_burst32_check(struct adis16475 *st)
|
|||
/*
|
||||
* In 32-bit mode we need extra 2 bytes for all gyro
|
||||
* and accel channels.
|
||||
* If the device has 32-bit timestamp value we need 2 extra
|
||||
* bytes for it.
|
||||
*/
|
||||
adis->burst_extra_len = 6 * sizeof(u16);
|
||||
adis->xfer[1].len += 6 * sizeof(u16);
|
||||
adis->burst_extra_len = (6 + timestamp32) * sizeof(u16);
|
||||
adis->xfer[1].len += (6 + timestamp32) * sizeof(u16);
|
||||
|
||||
dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d",
|
||||
adis->xfer[1].len);
|
||||
|
||||
|
|
@ -1249,7 +1568,7 @@ static void adis16475_burst32_check(struct adis16475 *st)
|
|||
|
||||
/* Remove the extra bits */
|
||||
adis->burst_extra_len = 0;
|
||||
adis->xfer[1].len -= 6 * sizeof(u16);
|
||||
adis->xfer[1].len -= (6 + timestamp32) * sizeof(u16);
|
||||
dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n",
|
||||
adis->xfer[1].len);
|
||||
}
|
||||
|
|
@ -1264,20 +1583,29 @@ static int adis16475_push_single_sample(struct iio_poll_func *pf)
|
|||
__be16 *buffer;
|
||||
u16 crc;
|
||||
bool valid;
|
||||
u8 crc_offset = 9;
|
||||
u16 burst_size = ADIS16475_BURST_MAX_DATA;
|
||||
u16 start_idx = (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 2 : 0;
|
||||
|
||||
/* offset until the first element after gyro and accel */
|
||||
const u8 offset = st->burst32 ? 13 : 7;
|
||||
|
||||
if (st->burst32) {
|
||||
crc_offset = (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 16 : 15;
|
||||
burst_size = adis->data->burst_max_len;
|
||||
}
|
||||
|
||||
ret = spi_sync(adis->spi, &adis->msg);
|
||||
if (ret)
|
||||
goto check_burst32;
|
||||
return ret;
|
||||
|
||||
buffer = adis->buffer;
|
||||
|
||||
crc = be16_to_cpu(buffer[offset + 2]);
|
||||
valid = adis16475_validate_crc(adis->buffer, crc, st->burst32);
|
||||
crc = be16_to_cpu(buffer[crc_offset]);
|
||||
valid = adis16475_validate_crc(adis->buffer, crc, burst_size, start_idx);
|
||||
if (!valid) {
|
||||
dev_err(&adis->spi->dev, "Invalid crc\n");
|
||||
goto check_burst32;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for_each_set_bit(bit, indio_dev->active_scan_mask,
|
||||
|
|
@ -1337,23 +1665,123 @@ static int adis16475_push_single_sample(struct iio_poll_func *pf)
|
|||
}
|
||||
}
|
||||
|
||||
/* There might not be a timestamp option for some devices. */
|
||||
iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp);
|
||||
check_burst32:
|
||||
/*
|
||||
* We only check the burst mode at the end of the current capture since
|
||||
* it takes a full data ready cycle for the device to update the burst
|
||||
* array.
|
||||
*/
|
||||
adis16475_burst32_check(st);
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t adis16475_trigger_handler(int irq, void *p)
|
||||
{
|
||||
struct iio_poll_func *pf = p;
|
||||
struct iio_dev *indio_dev = pf->indio_dev;
|
||||
struct adis16475 *st = iio_priv(indio_dev);
|
||||
|
||||
adis16475_push_single_sample(pf);
|
||||
/*
|
||||
* We only check the burst mode at the end of the current capture since
|
||||
* it takes a full data ready cycle for the device to update the burst
|
||||
* array.
|
||||
*/
|
||||
adis16475_burst32_check(st);
|
||||
|
||||
iio_trigger_notify_done(indio_dev->trig);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function updates the first tx byte from the adis message based on the
|
||||
* given burst request.
|
||||
*/
|
||||
static void adis16575_update_msg_for_burst(struct adis *adis, u8 burst_req)
|
||||
{
|
||||
unsigned int burst_max_length;
|
||||
u8 *tx;
|
||||
|
||||
if (adis->data->burst_max_len)
|
||||
burst_max_length = adis->data->burst_max_len;
|
||||
else
|
||||
burst_max_length = adis->data->burst_len + adis->burst_extra_len;
|
||||
|
||||
tx = adis->buffer + burst_max_length;
|
||||
tx[0] = ADIS_READ_REG(burst_req);
|
||||
}
|
||||
|
||||
static int adis16575_custom_burst_read(struct iio_poll_func *pf, u8 burst_req)
|
||||
{
|
||||
struct iio_dev *indio_dev = pf->indio_dev;
|
||||
struct adis16475 *st = iio_priv(indio_dev);
|
||||
struct adis *adis = &st->adis;
|
||||
|
||||
adis16575_update_msg_for_burst(adis, burst_req);
|
||||
|
||||
if (burst_req)
|
||||
return spi_sync(adis->spi, &adis->msg);
|
||||
|
||||
return adis16475_push_single_sample(pf);
|
||||
}
|
||||
|
||||
/*
|
||||
* This handler is meant to be used for devices which support burst readings
|
||||
* from FIFO (namely devices from adis1657x family).
|
||||
* In order to pop the FIFO the 0x68 0x00 FIFO pop burst request has to be sent.
|
||||
* If the previous device command was not a FIFO pop burst request, the FIFO pop
|
||||
* burst request will simply pop the FIFO without returning valid data.
|
||||
* For the nth consecutive burst request, thedevice will send the data popped
|
||||
* with the (n-1)th consecutive burst request.
|
||||
* In order to read the data which was popped previously, without popping the
|
||||
* FIFO, the 0x00 0x00 burst request has to be sent.
|
||||
* If after a 0x68 0x00 FIFO pop burst request, there is any other device access
|
||||
* different from a 0x68 0x00 or a 0x00 0x00 burst request, the FIFO data popped
|
||||
* previously will be lost.
|
||||
*/
|
||||
static irqreturn_t adis16475_trigger_handler_with_fifo(int irq, void *p)
|
||||
{
|
||||
struct iio_poll_func *pf = p;
|
||||
struct iio_dev *indio_dev = pf->indio_dev;
|
||||
struct adis16475 *st = iio_priv(indio_dev);
|
||||
struct adis *adis = &st->adis;
|
||||
int ret;
|
||||
u16 fifo_cnt, i;
|
||||
|
||||
adis_dev_lock(&st->adis);
|
||||
|
||||
ret = __adis_read_reg_16(adis, ADIS16575_REG_FIFO_CNT, &fifo_cnt);
|
||||
if (ret)
|
||||
goto unlock;
|
||||
|
||||
/*
|
||||
* If no sample is available, nothing can be read. This can happen if
|
||||
* a the used trigger has a higher frequency than the selected sample rate.
|
||||
*/
|
||||
if (!fifo_cnt)
|
||||
goto unlock;
|
||||
|
||||
/*
|
||||
* First burst request - FIFO pop: popped data will be returned in the
|
||||
* next burst request.
|
||||
*/
|
||||
ret = adis16575_custom_burst_read(pf, adis->data->burst_reg_cmd);
|
||||
if (ret)
|
||||
goto unlock;
|
||||
|
||||
for (i = 0; i < fifo_cnt - 1; i++) {
|
||||
ret = adis16475_push_single_sample(pf);
|
||||
if (ret)
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
/* FIFO read without popping */
|
||||
ret = adis16575_custom_burst_read(pf, 0);
|
||||
|
||||
unlock:
|
||||
/*
|
||||
* We only check the burst mode at the end of the current capture since
|
||||
* reading data from registers will impact the FIFO reading.
|
||||
*/
|
||||
adis16475_burst32_check(st);
|
||||
adis_dev_unlock(&st->adis);
|
||||
iio_trigger_notify_done(indio_dev->trig);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
|
|
@ -1368,6 +1796,15 @@ static int adis16475_config_sync_mode(struct adis16475 *st)
|
|||
u16 max_sample_rate = st->info->int_clk + 100;
|
||||
u16 val;
|
||||
|
||||
/* if available, enable 4khz internal clock */
|
||||
if (st->info->int_clk == 4000) {
|
||||
ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
|
||||
ADIS16575_SYNC_4KHZ_MASK,
|
||||
(u16)ADIS16575_SYNC_4KHZ(1));
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* default to internal clk */
|
||||
st->clk_freq = st->info->int_clk * 1000;
|
||||
|
||||
|
|
@ -1446,34 +1883,69 @@ static int adis16475_config_irq_pin(struct adis16475 *st)
|
|||
u8 polarity;
|
||||
struct spi_device *spi = st->adis.spi;
|
||||
|
||||
/*
|
||||
* It is possible to configure the data ready polarity. Furthermore, we
|
||||
* need to update the adis struct if we want data ready as active low.
|
||||
*/
|
||||
irq_type = irq_get_trigger_type(spi->irq);
|
||||
if (irq_type == IRQ_TYPE_EDGE_RISING) {
|
||||
polarity = 1;
|
||||
st->adis.irq_flag = IRQF_TRIGGER_RISING;
|
||||
} else if (irq_type == IRQ_TYPE_EDGE_FALLING) {
|
||||
polarity = 0;
|
||||
st->adis.irq_flag = IRQF_TRIGGER_FALLING;
|
||||
} else {
|
||||
dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n",
|
||||
irq_type);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
val = ADIS16475_MSG_CTRL_DR_POL(polarity);
|
||||
ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
|
||||
ADIS16475_MSG_CTRL_DR_POL_MASK, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
/*
|
||||
* There is a delay writing to any bits written to the MSC_CTRL
|
||||
* register. It should not be bigger than 200us, so 250 should be more
|
||||
* than enough!
|
||||
*/
|
||||
usleep_range(250, 260);
|
||||
if (st->adis.data->has_fifo) {
|
||||
/*
|
||||
* It is possible to configure the fifo watermark pin polarity.
|
||||
* Furthermore, we need to update the adis struct if we want the
|
||||
* watermark pin active low.
|
||||
*/
|
||||
if (irq_type == IRQ_TYPE_LEVEL_HIGH) {
|
||||
polarity = 1;
|
||||
st->adis.irq_flag = IRQF_TRIGGER_HIGH;
|
||||
} else if (irq_type == IRQ_TYPE_LEVEL_LOW) {
|
||||
polarity = 0;
|
||||
st->adis.irq_flag = IRQF_TRIGGER_LOW;
|
||||
} else {
|
||||
dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n",
|
||||
irq_type);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Configure the watermark pin polarity. */
|
||||
val = ADIS16575_WM_POL(polarity);
|
||||
ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL,
|
||||
ADIS16575_WM_POL_MASK, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Enable watermark interrupt pin. */
|
||||
ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL,
|
||||
ADIS16575_WM_EN_MASK,
|
||||
(u16)ADIS16575_WM_EN(1));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
} else {
|
||||
/*
|
||||
* It is possible to configure the data ready polarity. Furthermore, we
|
||||
* need to update the adis struct if we want data ready as active low.
|
||||
*/
|
||||
if (irq_type == IRQ_TYPE_EDGE_RISING) {
|
||||
polarity = 1;
|
||||
st->adis.irq_flag = IRQF_TRIGGER_RISING;
|
||||
} else if (irq_type == IRQ_TYPE_EDGE_FALLING) {
|
||||
polarity = 0;
|
||||
st->adis.irq_flag = IRQF_TRIGGER_FALLING;
|
||||
} else {
|
||||
dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n",
|
||||
irq_type);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
val = ADIS16475_MSG_CTRL_DR_POL(polarity);
|
||||
ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
|
||||
ADIS16475_MSG_CTRL_DR_POL_MASK, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
/*
|
||||
* There is a delay writing to any bits written to the MSC_CTRL
|
||||
* register. It should not be bigger than 200us, so 250 should be more
|
||||
* than enough!
|
||||
*/
|
||||
usleep_range(250, 260);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1484,6 +1956,7 @@ static int adis16475_probe(struct spi_device *spi)
|
|||
struct iio_dev *indio_dev;
|
||||
struct adis16475 *st;
|
||||
int ret;
|
||||
u16 val;
|
||||
|
||||
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
||||
if (!indio_dev)
|
||||
|
|
@ -1502,7 +1975,10 @@ static int adis16475_probe(struct spi_device *spi)
|
|||
indio_dev->name = st->info->name;
|
||||
indio_dev->channels = st->info->channels;
|
||||
indio_dev->num_channels = st->info->num_channels;
|
||||
indio_dev->info = &adis16475_info;
|
||||
if (st->adis.data->has_fifo)
|
||||
indio_dev->info = &adis16575_info;
|
||||
else
|
||||
indio_dev->info = &adis16475_info;
|
||||
indio_dev->modes = INDIO_DIRECT_MODE;
|
||||
|
||||
ret = __adis_initial_startup(&st->adis);
|
||||
|
|
@ -1517,10 +1993,26 @@ static int adis16475_probe(struct spi_device *spi)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
|
||||
adis16475_trigger_handler);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (st->adis.data->has_fifo) {
|
||||
ret = devm_adis_setup_buffer_and_trigger_with_attrs(&st->adis, indio_dev,
|
||||
adis16475_trigger_handler_with_fifo,
|
||||
&adis16475_buffer_ops,
|
||||
adis16475_fifo_attributes);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Update overflow behavior to always overwrite the oldest sample. */
|
||||
val = ADIS16575_OVERWRITE_OLDEST;
|
||||
ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL,
|
||||
ADIS16575_OVERFLOW_MASK, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else {
|
||||
ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
|
||||
adis16475_trigger_handler);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_iio_device_register(&spi->dev, indio_dev);
|
||||
if (ret)
|
||||
|
|
@ -1574,6 +2066,18 @@ static const struct of_device_id adis16475_of_match[] = {
|
|||
.data = &adis16475_chip_info[ADIS16507_2] },
|
||||
{ .compatible = "adi,adis16507-3",
|
||||
.data = &adis16475_chip_info[ADIS16507_3] },
|
||||
{ .compatible = "adi,adis16575-2",
|
||||
.data = &adis16475_chip_info[ADIS16575_2] },
|
||||
{ .compatible = "adi,adis16575-3",
|
||||
.data = &adis16475_chip_info[ADIS16575_3] },
|
||||
{ .compatible = "adi,adis16576-2",
|
||||
.data = &adis16475_chip_info[ADIS16576_2] },
|
||||
{ .compatible = "adi,adis16576-3",
|
||||
.data = &adis16475_chip_info[ADIS16576_3] },
|
||||
{ .compatible = "adi,adis16577-2",
|
||||
.data = &adis16475_chip_info[ADIS16577_2] },
|
||||
{ .compatible = "adi,adis16577-3",
|
||||
.data = &adis16475_chip_info[ADIS16577_3] },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, adis16475_of_match);
|
||||
|
|
@ -1600,6 +2104,12 @@ static const struct spi_device_id adis16475_ids[] = {
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{ "adis16507-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_1] },
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{ "adis16507-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_2] },
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{ "adis16507-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_3] },
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{ "adis16575-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16575_2] },
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{ "adis16575-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16575_3] },
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{ "adis16576-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16576_2] },
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{ "adis16576-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16576_3] },
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{ "adis16577-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16577_2] },
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{ "adis16577-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16577_3] },
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||||
{ }
|
||||
};
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||||
MODULE_DEVICE_TABLE(spi, adis16475_ids);
|
||||
|
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|
|||
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Reference in a new issue