ARM SoC device tree changes
These changes from 30 individual branches for the most part update device tree files, but there are also a few source code changes that have crept in this time, usually in order to atomically move over a driver from using hardcoded data to DT probing. A number of platforms change their DT files to use the C preprocessor, which is causing a bit of churn, but that is hopefully only this once. There are a few conflicts with the other branches unfortunately: * in exynos5440.dtsi and kirkwood-6281.dtsi, device nodes are added from multiple branches. Need to be careful to have the right set of closing braces as git gets this one wrong. * In kirkwood.dtsi, one 'ranges' line got split into two lines, while another line got added. Order of the lines does not matter. * in sama5d3.dtsi, some cleanup was merged the wrong way, causing a bogus conflict. We want the 'dmas' and 'dma-names' properties to get added here. * Two lines got removed independently in arch/arm/mach-mxs/mach-mxs.c * Contents get added independently in arch/arm/mach-omap2/cclock33xx_data.c -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUdLnpGCrR//JCVInAQI50RAAsXbH1SGvjKJemXhRkFloPDYpCbgdDUFr ChUbjNV1xsY/jaNCfMa5/Qo7lgz/Ot7BpJef9fZn7ret+dc7nchqe/4iIkAokAUh E4ao9D1dP5aAA0ihdbSQHCZtR/0SUR81h6BoOVuo/1mvEiBaFbWAeYe8/6LJd9II OU1w9bDmjfZWYFUXs+j2VF76ueZQ+kz69XDKZUGtkqN76m1AL8lGDurj5jxvyllF VJns8d9q2nr2q9PferfajK6rkOIPaTpwKblxZHUgobCyOitZaiZM0NgF733TsNM6 HXmhDhkcn7T81+SiHVfigJ/nxo9UgU4zNJCODF3WZIwGIj3FbxvCOpdCYi2NhCO8 oLcgDk57tpoKpB3gvAmYVQHP9FIepFa/WAWyPIADA7PkpYrwgc4v+cLEHXpd8SRv viLLIa5QuNdMeaK+Md9OKmKZFd7uFD9jiMtmdm6IpEVDDjMgoteb2XSoEtNebmtY MfbW4okn118a2dFKKaPTKcXVW/a5FRp2JGfB0A58RQHaJWj3JsY1bFn/xWPEpTOA IWB/HHMln0LYTL2AXN9HcaL1jnGI1Wq5eWBurX+cXQ/ij1A6jfoRKYglx7AQqOHj iWcGYtKLLJCgiWFnLSwcljZhfoYr0/z7rhns6yo7/vhN0riy+M84OgN4HbAmUzc1 Bgy9PnJTNo8= =8PtJ -----END PGP SIGNATURE----- Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree changes from Arnd Bergmann: "These changes from 30 individual branches for the most part update device tree files, but there are also a few source code changes that have crept in this time, usually in order to atomically move over a driver from using hardcoded data to DT probing. A number of platforms change their DT files to use the C preprocessor, which is causing a bit of churn, but that is hopefully only this once" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits) ARM: at91: dt: rm9200ek: add spi support ARM: at91: dt: rm9200: add spi support ARM: at91/DT: at91sam9n12: add SPI DMA client infos ARM: at91/DT: sama5d3: add SPI DMA client infos ARM: at91/DT: fix SPI compatibility string ARM: Kirkwood: Fix the internal register ranges translation ARM: dts: bcm281xx: change comment to C89 style ARM: mmc: bcm281xx SDHCI driver (dt mods) ARM: nomadik: add the new clocks to the device tree clk: nomadik: implement the Nomadik clocks properly ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency ARM: dts: omap4-panda: Fix DVI EDID reads ARM: dts: omap4-panda: Add USB Host support arm: mvebu: enable mini-PCIe connectors on Armada 370 RD ARM: shmobile: irqpin: add a DT property to enable masking on parent ARM: dts: AM43x EPOS EVM support ARM: dts: OMAP5: Add bandgap DT entry ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ...
This commit is contained in:
Linus Torvalds
commit
ee1a8d402e
297 changed files with 15464 additions and 3271 deletions
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|
@ -56,3 +56,6 @@ Boards:
|
|||
|
||||
- OMAP5 EVM : Evaluation Module
|
||||
compatible = "ti,omap5-evm", "ti,omap5"
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- AM43x EPOS EVM
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||||
compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
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||||
|
|
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@ -3,6 +3,11 @@ ST-Ericsson Nomadik Device Tree Bindings
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For various board the "board" node may contain specific properties
|
||||
that pertain to this particular board, such as board-specific GPIOs.
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Required root node property: src
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- Nomadik System and reset controller used for basic chip control, clock
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and reset line control.
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- compatible: must be "stericsson,nomadik,src"
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Boards with the Nomadik SoC include:
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S8815 "MiniKit" manufactured by Calao Systems:
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|
|
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49
Documentation/devicetree/bindings/bus/imx-weim.txt
Normal file
49
Documentation/devicetree/bindings/bus/imx-weim.txt
Normal file
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@ -0,0 +1,49 @@
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Device tree bindings for i.MX Wireless External Interface Module (WEIM)
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The term "wireless" does not imply that the WEIM is literally an interface
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without wires. It simply means that this module was originally designed for
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wireless and mobile applications that use low-power technology.
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The actual devices are instantiated from the child nodes of a WEIM node.
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Required properties:
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- compatible: Should be set to "fsl,imx6q-weim"
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- reg: A resource specifier for the register space
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(see the example below)
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- clocks: the clock, see the example below.
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- #address-cells: Must be set to 2 to allow memory address translation
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- #size-cells: Must be set to 1 to allow CS address passing
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- ranges: Must be set up to reflect the memory layout with four
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integer values for each chip-select line in use:
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<cs-number> 0 <physical address of mapping> <size>
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Timing property for child nodes. It is mandatory, not optional.
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- fsl,weim-cs-timing: The timing array, contains 6 timing values for the
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child node. We can get the CS index from the child
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node's "reg" property. This property contains the values
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for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
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EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
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Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
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weim: weim@021b8000 {
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compatible = "fsl,imx6q-weim";
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reg = <0x021b8000 0x4000>;
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clocks = <&clks 196>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x08000000>;
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nor@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x02000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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bank-width = <2>;
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fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
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0x0000c000 0x1404a38e 0x00000000>;
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};
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};
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@ -9,6 +9,9 @@ Required properties:
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"altr,socfpga-pll-clock" - for a PLL clock
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"altr,socfpga-perip-clock" - The peripheral clock divided from the
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PLL clock.
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"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
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can get gated.
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- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
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- clocks : shall be the input parent clock phandle for the clock. This is
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either an oscillator or a pll output.
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@ -16,3 +19,7 @@ Required properties:
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|||
|
||||
Optional properties:
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||||
- fixed-divider : If clocks have a fixed divider value, use this property.
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||||
- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
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||||
and the bit index.
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- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
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and width.
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|
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@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable.
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sclk_spi0_isp 174 Exynos4x12
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sclk_spi1_isp 175 Exynos4x12
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sclk_uart_isp 176 Exynos4x12
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sclk_fimg2d 177
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[Peripheral Clock Gates]
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@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable.
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smmu_mfcl 274
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smmu_mfcr 275
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g3d 276
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g2d 277 Exynos4210
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g2d 277
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rotator 278 Exynos4210
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mdma 279 Exynos4210
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smmu_g2d 280 Exynos4210
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|
|
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@ -12,253 +12,9 @@ Required properties :
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|||
- clocks : Should contain phandle and clock specifiers for two clocks:
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the 32 KHz "32k_in", and the board-specific oscillator "osc".
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- #clock-cells : Should be 1.
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In clock consumers, this cell represents the clock ID exposed by the CAR.
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|
||||
The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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||||
registers. These IDs often match those in the CAR's RST_DEVICES registers,
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but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
this case, those clocks are assigned IDs above 160 in order to highlight
|
||||
this issue. Implementations that interpret these clock IDs as bit values
|
||||
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
explicitly handle these special cases.
|
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|
||||
The balance of the clocks controlled by the CAR are assigned IDs of 160 and
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above.
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0 unassigned
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||||
1 unassigned
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||||
2 unassigned
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||||
3 unassigned
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4 rtc
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5 timer
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6 uarta
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7 unassigned (register bit affects uartb and vfir)
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8 unassigned
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9 sdmmc2
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10 unassigned (register bit affects spdif_in and spdif_out)
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11 i2s1
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12 i2c1
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13 ndflash
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14 sdmmc1
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15 sdmmc4
|
||||
16 unassigned
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||||
17 pwm
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||||
18 i2s2
|
||||
19 epp
|
||||
20 unassigned (register bit affects vi and vi_sensor)
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||||
21 2d
|
||||
22 usbd
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23 isp
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||||
24 3d
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||||
25 unassigned
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||||
26 disp2
|
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27 disp1
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||||
28 host1x
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29 vcp
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30 i2s0
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31 unassigned
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||||
32 unassigned
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||||
33 unassigned
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||||
34 apbdma
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||||
35 unassigned
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||||
36 kbc
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37 unassigned
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38 unassigned
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||||
39 unassigned (register bit affects fuse and fuse_burn)
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40 kfuse
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41 sbc1
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42 nor
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43 unassigned
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44 sbc2
|
||||
45 unassigned
|
||||
46 sbc3
|
||||
47 i2c5
|
||||
48 dsia
|
||||
49 unassigned
|
||||
50 mipi
|
||||
51 hdmi
|
||||
52 csi
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||||
53 unassigned
|
||||
54 i2c2
|
||||
55 uartc
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||||
56 mipi-cal
|
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57 emc
|
||||
58 usb2
|
||||
59 usb3
|
||||
60 msenc
|
||||
61 vde
|
||||
62 bsea
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63 bsev
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|
||||
64 unassigned
|
||||
65 uartd
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||||
66 unassigned
|
||||
67 i2c3
|
||||
68 sbc4
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||||
69 sdmmc3
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||||
70 unassigned
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||||
71 owr
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||||
72 afi
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||||
73 csite
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||||
74 unassigned
|
||||
75 unassigned
|
||||
76 la
|
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77 trace
|
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78 soc_therm
|
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79 dtv
|
||||
80 ndspeed
|
||||
81 i2cslow
|
||||
82 dsib
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||||
83 tsec
|
||||
84 unassigned
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||||
85 unassigned
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||||
86 unassigned
|
||||
87 unassigned
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||||
88 unassigned
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||||
89 xusb_host
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||||
90 unassigned
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||||
91 msenc
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92 csus
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||||
93 unassigned
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||||
94 unassigned
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||||
95 unassigned (bit affects xusb_dev and xusb_dev_src)
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||||
96 unassigned
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||||
97 unassigned
|
||||
98 unassigned
|
||||
99 mselect
|
||||
100 tsensor
|
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101 i2s3
|
||||
102 i2s4
|
||||
103 i2c4
|
||||
104 sbc5
|
||||
105 sbc6
|
||||
106 d_audio
|
||||
107 apbif
|
||||
108 dam0
|
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109 dam1
|
||||
110 dam2
|
||||
111 hda2codec_2x
|
||||
112 unassigned
|
||||
113 audio0_2x
|
||||
114 audio1_2x
|
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115 audio2_2x
|
||||
116 audio3_2x
|
||||
117 audio4_2x
|
||||
118 spdif_2x
|
||||
119 actmon
|
||||
120 extern1
|
||||
121 extern2
|
||||
122 extern3
|
||||
123 unassigned
|
||||
124 unassigned
|
||||
125 hda
|
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126 unassigned
|
||||
127 se
|
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|
||||
128 hda2hdmi
|
||||
129 unassigned
|
||||
130 unassigned
|
||||
131 unassigned
|
||||
132 unassigned
|
||||
133 unassigned
|
||||
134 unassigned
|
||||
135 unassigned
|
||||
136 unassigned
|
||||
137 unassigned
|
||||
138 unassigned
|
||||
139 unassigned
|
||||
140 unassigned
|
||||
141 unassigned
|
||||
142 unassigned
|
||||
143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
|
||||
xusb_host_src and xusb_ss_src)
|
||||
144 cilab
|
||||
145 cilcd
|
||||
146 cile
|
||||
147 dsialp
|
||||
148 dsiblp
|
||||
149 unassigned
|
||||
150 dds
|
||||
151 unassigned
|
||||
152 dp2
|
||||
153 amx
|
||||
154 adx
|
||||
155 unassigned (bit affects dfll_ref and dfll_soc)
|
||||
156 xusb_ss
|
||||
|
||||
192 uartb
|
||||
193 vfir
|
||||
194 spdif_in
|
||||
195 spdif_out
|
||||
196 vi
|
||||
197 vi_sensor
|
||||
198 fuse
|
||||
199 fuse_burn
|
||||
200 clk_32k
|
||||
201 clk_m
|
||||
202 clk_m_div2
|
||||
203 clk_m_div4
|
||||
204 pll_ref
|
||||
205 pll_c
|
||||
206 pll_c_out1
|
||||
207 pll_c2
|
||||
208 pll_c3
|
||||
209 pll_m
|
||||
210 pll_m_out1
|
||||
211 pll_p
|
||||
212 pll_p_out1
|
||||
213 pll_p_out2
|
||||
214 pll_p_out3
|
||||
215 pll_p_out4
|
||||
216 pll_a
|
||||
217 pll_a_out0
|
||||
218 pll_d
|
||||
219 pll_d_out0
|
||||
220 pll_d2
|
||||
221 pll_d2_out0
|
||||
222 pll_u
|
||||
223 pll_u_480M
|
||||
224 pll_u_60M
|
||||
225 pll_u_48M
|
||||
226 pll_u_12M
|
||||
227 pll_x
|
||||
228 pll_x_out0
|
||||
229 pll_re_vco
|
||||
230 pll_re_out
|
||||
231 pll_e_out0
|
||||
232 spdif_in_sync
|
||||
233 i2s0_sync
|
||||
234 i2s1_sync
|
||||
235 i2s2_sync
|
||||
236 i2s3_sync
|
||||
237 i2s4_sync
|
||||
238 vimclk_sync
|
||||
239 audio0
|
||||
240 audio1
|
||||
241 audio2
|
||||
242 audio3
|
||||
243 audio4
|
||||
244 spdif
|
||||
245 clk_out_1
|
||||
246 clk_out_2
|
||||
247 clk_out_3
|
||||
248 blink
|
||||
252 xusb_host_src
|
||||
253 xusb_falcon_src
|
||||
254 xusb_fs_src
|
||||
255 xusb_ss_src
|
||||
256 xusb_dev_src
|
||||
257 xusb_dev
|
||||
258 xusb_hs_src
|
||||
259 sclk
|
||||
260 hclk
|
||||
261 pclk
|
||||
262 cclk_g
|
||||
263 cclk_lp
|
||||
264 dfll_ref
|
||||
265 dfll_soc
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra114-car.h>.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
|
|
@ -270,7 +26,7 @@ Example SoC include file:
|
|||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car 58>; /* usb2 */
|
||||
clocks = <&tegra_car TEGRA114_CLK_USB2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,155 +12,9 @@ Required properties :
|
|||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the CAR.
|
||||
|
||||
The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
this case, those clocks are assigned IDs above 95 in order to highlight
|
||||
this issue. Implementations that interpret these clock IDs as bit values
|
||||
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
explicitly handle these special cases.
|
||||
|
||||
The balance of the clocks controlled by the CAR are assigned IDs of 96 and
|
||||
above.
|
||||
|
||||
0 cpu
|
||||
1 unassigned
|
||||
2 unassigned
|
||||
3 ac97
|
||||
4 rtc
|
||||
5 tmr
|
||||
6 uart1
|
||||
7 unassigned (register bit affects uart2 and vfir)
|
||||
8 gpio
|
||||
9 sdmmc2
|
||||
10 unassigned (register bit affects spdif_in and spdif_out)
|
||||
11 i2s1
|
||||
12 i2c1
|
||||
13 ndflash
|
||||
14 sdmmc1
|
||||
15 sdmmc4
|
||||
16 twc
|
||||
17 pwm
|
||||
18 i2s2
|
||||
19 epp
|
||||
20 unassigned (register bit affects vi and vi_sensor)
|
||||
21 2d
|
||||
22 usbd
|
||||
23 isp
|
||||
24 3d
|
||||
25 ide
|
||||
26 disp2
|
||||
27 disp1
|
||||
28 host1x
|
||||
29 vcp
|
||||
30 unassigned
|
||||
31 cache2
|
||||
|
||||
32 mem
|
||||
33 ahbdma
|
||||
34 apbdma
|
||||
35 unassigned
|
||||
36 kbc
|
||||
37 stat_mon
|
||||
38 pmc
|
||||
39 fuse
|
||||
40 kfuse
|
||||
41 sbc1
|
||||
42 snor
|
||||
43 spi1
|
||||
44 sbc2
|
||||
45 xio
|
||||
46 sbc3
|
||||
47 dvc
|
||||
48 dsi
|
||||
49 unassigned (register bit affects tvo and cve)
|
||||
50 mipi
|
||||
51 hdmi
|
||||
52 csi
|
||||
53 tvdac
|
||||
54 i2c2
|
||||
55 uart3
|
||||
56 unassigned
|
||||
57 emc
|
||||
58 usb2
|
||||
59 usb3
|
||||
60 mpe
|
||||
61 vde
|
||||
62 bsea
|
||||
63 bsev
|
||||
|
||||
64 speedo
|
||||
65 uart4
|
||||
66 uart5
|
||||
67 i2c3
|
||||
68 sbc4
|
||||
69 sdmmc3
|
||||
70 pcie
|
||||
71 owr
|
||||
72 afi
|
||||
73 csite
|
||||
74 unassigned
|
||||
75 avpucq
|
||||
76 la
|
||||
77 unassigned
|
||||
78 unassigned
|
||||
79 unassigned
|
||||
80 unassigned
|
||||
81 unassigned
|
||||
82 unassigned
|
||||
83 unassigned
|
||||
84 irama
|
||||
85 iramb
|
||||
86 iramc
|
||||
87 iramd
|
||||
88 cram2
|
||||
89 audio_2x a/k/a audio_2x_sync_clk
|
||||
90 clk_d
|
||||
91 unassigned
|
||||
92 sus
|
||||
93 cdev2
|
||||
94 cdev1
|
||||
95 unassigned
|
||||
|
||||
96 uart2
|
||||
97 vfir
|
||||
98 spdif_in
|
||||
99 spdif_out
|
||||
100 vi
|
||||
101 vi_sensor
|
||||
102 tvo
|
||||
103 cve
|
||||
104 osc
|
||||
105 clk_32k a/k/a clk_s
|
||||
106 clk_m
|
||||
107 sclk
|
||||
108 cclk
|
||||
109 hclk
|
||||
110 pclk
|
||||
111 blink
|
||||
112 pll_a
|
||||
113 pll_a_out0
|
||||
114 pll_c
|
||||
115 pll_c_out1
|
||||
116 pll_d
|
||||
117 pll_d_out0
|
||||
118 pll_e
|
||||
119 pll_m
|
||||
120 pll_m_out1
|
||||
121 pll_p
|
||||
122 pll_p_out1
|
||||
123 pll_p_out2
|
||||
124 pll_p_out3
|
||||
125 pll_p_out4
|
||||
126 pll_s
|
||||
127 pll_u
|
||||
128 pll_x
|
||||
129 cop a/k/a avp
|
||||
130 audio a/k/a audio_sync_clk
|
||||
131 pll_ref
|
||||
132 twd
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra20-car.h>.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
|
|
@ -172,7 +26,7 @@ Example SoC include file:
|
|||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car 58>; /* usb2 */
|
||||
clocks = <&tegra_car TEGRA20_CLK_USB2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,212 +12,9 @@ Required properties :
|
|||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the CAR.
|
||||
|
||||
The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
this case, those clocks are assigned IDs above 160 in order to highlight
|
||||
this issue. Implementations that interpret these clock IDs as bit values
|
||||
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
explicitly handle these special cases.
|
||||
|
||||
The balance of the clocks controlled by the CAR are assigned IDs of 160 and
|
||||
above.
|
||||
|
||||
0 cpu
|
||||
1 unassigned
|
||||
2 unassigned
|
||||
3 unassigned
|
||||
4 rtc
|
||||
5 timer
|
||||
6 uarta
|
||||
7 unassigned (register bit affects uartb and vfir)
|
||||
8 gpio
|
||||
9 sdmmc2
|
||||
10 unassigned (register bit affects spdif_in and spdif_out)
|
||||
11 i2s1
|
||||
12 i2c1
|
||||
13 ndflash
|
||||
14 sdmmc1
|
||||
15 sdmmc4
|
||||
16 unassigned
|
||||
17 pwm
|
||||
18 i2s2
|
||||
19 epp
|
||||
20 unassigned (register bit affects vi and vi_sensor)
|
||||
21 2d
|
||||
22 usbd
|
||||
23 isp
|
||||
24 3d
|
||||
25 unassigned
|
||||
26 disp2
|
||||
27 disp1
|
||||
28 host1x
|
||||
29 vcp
|
||||
30 i2s0
|
||||
31 cop_cache
|
||||
|
||||
32 mc
|
||||
33 ahbdma
|
||||
34 apbdma
|
||||
35 unassigned
|
||||
36 kbc
|
||||
37 statmon
|
||||
38 pmc
|
||||
39 unassigned (register bit affects fuse and fuse_burn)
|
||||
40 kfuse
|
||||
41 sbc1
|
||||
42 nor
|
||||
43 unassigned
|
||||
44 sbc2
|
||||
45 unassigned
|
||||
46 sbc3
|
||||
47 i2c5
|
||||
48 dsia
|
||||
49 unassigned (register bit affects cve and tvo)
|
||||
50 mipi
|
||||
51 hdmi
|
||||
52 csi
|
||||
53 tvdac
|
||||
54 i2c2
|
||||
55 uartc
|
||||
56 unassigned
|
||||
57 emc
|
||||
58 usb2
|
||||
59 usb3
|
||||
60 mpe
|
||||
61 vde
|
||||
62 bsea
|
||||
63 bsev
|
||||
|
||||
64 speedo
|
||||
65 uartd
|
||||
66 uarte
|
||||
67 i2c3
|
||||
68 sbc4
|
||||
69 sdmmc3
|
||||
70 pcie
|
||||
71 owr
|
||||
72 afi
|
||||
73 csite
|
||||
74 pciex
|
||||
75 avpucq
|
||||
76 la
|
||||
77 unassigned
|
||||
78 unassigned
|
||||
79 dtv
|
||||
80 ndspeed
|
||||
81 i2cslow
|
||||
82 dsib
|
||||
83 unassigned
|
||||
84 irama
|
||||
85 iramb
|
||||
86 iramc
|
||||
87 iramd
|
||||
88 cram2
|
||||
89 unassigned
|
||||
90 audio_2x a/k/a audio_2x_sync_clk
|
||||
91 unassigned
|
||||
92 csus
|
||||
93 cdev2
|
||||
94 cdev1
|
||||
95 unassigned
|
||||
|
||||
96 cpu_g
|
||||
97 cpu_lp
|
||||
98 3d2
|
||||
99 mselect
|
||||
100 tsensor
|
||||
101 i2s3
|
||||
102 i2s4
|
||||
103 i2c4
|
||||
104 sbc5
|
||||
105 sbc6
|
||||
106 d_audio
|
||||
107 apbif
|
||||
108 dam0
|
||||
109 dam1
|
||||
110 dam2
|
||||
111 hda2codec_2x
|
||||
112 atomics
|
||||
113 audio0_2x
|
||||
114 audio1_2x
|
||||
115 audio2_2x
|
||||
116 audio3_2x
|
||||
117 audio4_2x
|
||||
118 audio5_2x
|
||||
119 actmon
|
||||
120 extern1
|
||||
121 extern2
|
||||
122 extern3
|
||||
123 sata_oob
|
||||
124 sata
|
||||
125 hda
|
||||
127 se
|
||||
128 hda2hdmi
|
||||
129 sata_cold
|
||||
|
||||
160 uartb
|
||||
161 vfir
|
||||
162 spdif_in
|
||||
163 spdif_out
|
||||
164 vi
|
||||
165 vi_sensor
|
||||
166 fuse
|
||||
167 fuse_burn
|
||||
168 cve
|
||||
169 tvo
|
||||
|
||||
170 clk_32k
|
||||
171 clk_m
|
||||
172 clk_m_div2
|
||||
173 clk_m_div4
|
||||
174 pll_ref
|
||||
175 pll_c
|
||||
176 pll_c_out1
|
||||
177 pll_m
|
||||
178 pll_m_out1
|
||||
179 pll_p
|
||||
180 pll_p_out1
|
||||
181 pll_p_out2
|
||||
182 pll_p_out3
|
||||
183 pll_p_out4
|
||||
184 pll_a
|
||||
185 pll_a_out0
|
||||
186 pll_d
|
||||
187 pll_d_out0
|
||||
188 pll_d2
|
||||
189 pll_d2_out0
|
||||
190 pll_u
|
||||
191 pll_x
|
||||
192 pll_x_out0
|
||||
193 pll_e
|
||||
194 spdif_in_sync
|
||||
195 i2s0_sync
|
||||
196 i2s1_sync
|
||||
197 i2s2_sync
|
||||
198 i2s3_sync
|
||||
199 i2s4_sync
|
||||
200 vimclk
|
||||
201 audio0
|
||||
202 audio1
|
||||
203 audio2
|
||||
204 audio3
|
||||
205 audio4
|
||||
206 audio5
|
||||
207 clk_out_1 (extern1)
|
||||
208 clk_out_2 (extern2)
|
||||
209 clk_out_3 (extern3)
|
||||
210 sclk
|
||||
211 blink
|
||||
212 cclk_g
|
||||
213 cclk_lp
|
||||
214 twd
|
||||
215 cml0
|
||||
216 cml1
|
||||
217 hclk
|
||||
218 pclk
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra30-car.h>.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
|
|
@ -229,7 +26,7 @@ Example SoC include file:
|
|||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car 58>; /* usb2 */
|
||||
clocks = <&tegra_car TEGRA30_CLK_USB2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
104
Documentation/devicetree/bindings/clock/st,nomadik.txt
Normal file
104
Documentation/devicetree/bindings/clock/st,nomadik.txt
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
ST Microelectronics Nomadik SRC System Reset and Control
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
The Nomadik SRC controller is responsible of controlling chrystals,
|
||||
PLLs and clock gates.
|
||||
|
||||
Required properties for the SRC node:
|
||||
- compatible: must be "stericsson,nomadik-src"
|
||||
- reg: must contain the SRC register base and size
|
||||
|
||||
Optional properties for the SRC node:
|
||||
- disable-sxtalo: if present this will disable the SXTALO
|
||||
i.e. the driver output for the slow 32kHz chrystal, if the
|
||||
board has its own circuitry for providing this oscillator
|
||||
- disable-mxtal: if present this will disable the MXTALO,
|
||||
i.e. the driver output for the main (~19.2 MHz) chrystal,
|
||||
if the board has its own circuitry for providing this
|
||||
osciallator
|
||||
|
||||
|
||||
PLL nodes: these nodes represent the two PLLs on the system,
|
||||
which should both have the main chrystal, represented as a
|
||||
fixed frequency clock, as parent.
|
||||
|
||||
Required properties for the two PLL nodes:
|
||||
- compatible: must be "st,nomadik-pll-clock"
|
||||
- clock-cells: must be 0
|
||||
- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
|
||||
- clocks: this clock will have main chrystal as parent
|
||||
|
||||
|
||||
HCLK nodes: these represent the clock gates on individual
|
||||
lines from the HCLK clock tree and the gate for individual
|
||||
lines from the PCLK clock tree.
|
||||
|
||||
Requires properties for the HCLK nodes:
|
||||
- compatible: must be "st,nomadik-hclk-clock"
|
||||
- clock-cells: must be 0
|
||||
- clock-id: must be the clock ID from 0 to 63 according to
|
||||
this table:
|
||||
|
||||
0: HCLKDMA0
|
||||
1: HCLKSMC
|
||||
2: HCLKSDRAM
|
||||
3: HCLKDMA1
|
||||
4: HCLKCLCD
|
||||
5: PCLKIRDA
|
||||
6: PCLKSSP
|
||||
7: PCLKUART0
|
||||
8: PCLKSDI
|
||||
9: PCLKI2C0
|
||||
10: PCLKI2C1
|
||||
11: PCLKUART1
|
||||
12: PCLMSP0
|
||||
13: HCLKUSB
|
||||
14: HCLKDIF
|
||||
15: HCLKSAA
|
||||
16: HCLKSVA
|
||||
17: PCLKHSI
|
||||
18: PCLKXTI
|
||||
19: PCLKUART2
|
||||
20: PCLKMSP1
|
||||
21: PCLKMSP2
|
||||
22: PCLKOWM
|
||||
23: HCLKHPI
|
||||
24: PCLKSKE
|
||||
25: PCLKHSEM
|
||||
26: HCLK3D
|
||||
27: HCLKHASH
|
||||
28: HCLKCRYP
|
||||
29: PCLKMSHC
|
||||
30: HCLKUSBM
|
||||
31: HCLKRNG
|
||||
(32, 33, 34, 35 RESERVED)
|
||||
36: CLDCLK
|
||||
37: IRDACLK
|
||||
38: SSPICLK
|
||||
39: UART0CLK
|
||||
40: SDICLK
|
||||
41: I2C0CLK
|
||||
42: I2C1CLK
|
||||
43: UART1CLK
|
||||
44: MSPCLK0
|
||||
45: USBCLK
|
||||
46: DIFCLK
|
||||
47: IPI2CCLK
|
||||
48: IPBMCCLK
|
||||
49: HSICLKRX
|
||||
50: HSICLKTX
|
||||
51: UART2CLK
|
||||
52: MSPCLK1
|
||||
53: MSPCLK2
|
||||
54: OWMCLK
|
||||
(55 RESERVED)
|
||||
56: SKECLK
|
||||
(57 RESERVED)
|
||||
58: 3DCLK
|
||||
59: PCLKMSP3
|
||||
60: MSPCLK3
|
||||
61: MSHCCLK
|
||||
62: USBMCLK
|
||||
63: RNGCCLK
|
||||
|
|
@ -10,11 +10,16 @@ Required properties:
|
|||
mapped region.
|
||||
|
||||
- interrupts : G2D interrupt number to the CPU.
|
||||
- clocks : from common clock binding: handle to G2D clocks.
|
||||
- clock-names : from common clock binding: must contain "sclk_fimg2d" and
|
||||
"fimg2d", corresponding to entries in the clocks property.
|
||||
|
||||
Example:
|
||||
g2d@12800000 {
|
||||
compatible = "samsung,s5pv210-g2d";
|
||||
reg = <0x12800000 0x1000>;
|
||||
interrupts = <0 89 0>;
|
||||
clocks = <&clock 177>, <&clock 277>;
|
||||
clock-names = "sclk_fimg2d", "fimg2d";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
DT bindings for the R-/SH-Mobile irqpin controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: has to be "renesas,intc-irqpin"
|
||||
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
|
||||
interrupts.txt in this directory
|
||||
|
||||
Optional properties:
|
||||
|
||||
- any properties, listed in interrupts.txt, and any standard resource allocation
|
||||
properties
|
||||
- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
|
||||
if different from the default 4 bits
|
||||
- control-parent: disable and enable interrupts on the parent interrupt
|
||||
controller, needed for some broken implementations
|
||||
|
|
@ -15,6 +15,9 @@ Required properties:
|
|||
mapped region.
|
||||
|
||||
- interrupts : MFC interrupt number to the CPU.
|
||||
- clocks : from common clock binding: handle to mfc clocks.
|
||||
- clock-names : from common clock binding: must contain "sclk_mfc" and "mfc",
|
||||
corresponding to entries in the clocks property.
|
||||
|
||||
- samsung,mfc-r : Base address of the first memory bank used by MFC
|
||||
for DMA contiguous memory allocation and its size.
|
||||
|
|
@ -34,6 +37,8 @@ mfc: codec@13400000 {
|
|||
reg = <0x13400000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
clocks = <&clock 170>, <&clock 273>;
|
||||
clock-names = "sclk_mfc", "mfc";
|
||||
};
|
||||
|
||||
Board specific DT entry:
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@ ab8500 {
|
|||
"USB_LINK_STATUS",
|
||||
"USB_ADP_PROBE_PLUG",
|
||||
"USB_ADP_PROBE_UNPLUG";
|
||||
vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
|
||||
vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
|
||||
v-ape-supply = <&db8500_vape_reg>;
|
||||
musb_1v8-supply = <&db8500_vsmps2_reg>;
|
||||
};
|
||||
|
|
|
|||
16
Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
Normal file
16
Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
Broadcom BCM281xx SDHCI
|
||||
|
||||
This file documents differences between the core properties in mmc.txt
|
||||
and the properties present in the bcm281xx SDHCI
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "bcm,kona-sdhci"
|
||||
|
||||
Example:
|
||||
|
||||
sdio2: sdio@0x3f1a0000 {
|
||||
compatible = "bcm,kona-sdhci";
|
||||
reg = <0x3f1a0000 0x10000>;
|
||||
interrupts = <0x0 74 0x4>;
|
||||
};
|
||||
|
||||
|
|
@ -58,7 +58,7 @@ Some requirements for using fsl,imx-pinctrl binding:
|
|||
|
||||
Examples:
|
||||
usdhc@0219c000 { /* uSDHC4 */
|
||||
fsl,card-wired;
|
||||
non-removable;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -21,8 +21,18 @@ Required Properties:
|
|||
|
||||
- gpio-controller: identifies the node as a gpio controller and pin bank.
|
||||
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
|
||||
binding is used, the amount of cells must be specified as 2. See generic
|
||||
GPIO binding documentation for description of particular cells.
|
||||
binding is used, the amount of cells must be specified as 2. See the below
|
||||
mentioned gpio binding representation for description of particular cells.
|
||||
|
||||
Eg: <&gpx2 6 0>
|
||||
<[phandle of the gpio controller node]
|
||||
[pin number within the gpio controller]
|
||||
[flags]>
|
||||
|
||||
Values for gpio specifier:
|
||||
- Pin number: is a value between 0 to 7.
|
||||
- Flags: 0 - Active High
|
||||
1 - Active Low
|
||||
|
||||
- Pin mux/config groups as child nodes: The pin mux (selecting pin function
|
||||
mode) and pin config (pull up/down, driver strength) settings are represented
|
||||
|
|
@ -266,3 +276,33 @@ Example 4: Set up the default pin state for uart controller.
|
|||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
}
|
||||
|
||||
Example 5: A display port client node that supports 'default' pinctrl state
|
||||
and gpio binding.
|
||||
|
||||
display-port-controller {
|
||||
/* ... */
|
||||
|
||||
samsung,hpd-gpio = <&gpx2 6 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dp_hpd>;
|
||||
};
|
||||
|
||||
Example 6: Request the gpio for display port controller
|
||||
|
||||
static int exynos_dp_probe(struct platform_device *pdev)
|
||||
{
|
||||
int hpd_gpio, ret;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *dp_node = dev->of_node;
|
||||
|
||||
/* ... */
|
||||
|
||||
hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0);
|
||||
|
||||
/* ... */
|
||||
|
||||
ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN,
|
||||
"hpd_gpio");
|
||||
/* ... */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -48,3 +48,37 @@ Example:
|
|||
clocks = <&clock 285>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
DWC3
|
||||
Required properties:
|
||||
- compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3
|
||||
controller.
|
||||
- #address-cells, #size-cells : should be '1' if the device has sub-nodes
|
||||
with 'reg' property.
|
||||
- ranges: allows valid 1:1 translation between child's address space and
|
||||
parent's address space
|
||||
- clocks: Clock IDs array as required by the controller.
|
||||
- clock-names: names of clocks correseponding to IDs in the clock property
|
||||
|
||||
Sub-nodes:
|
||||
The dwc3 core should be added as subnode to Exynos dwc3 glue.
|
||||
- dwc3 :
|
||||
The binding details of dwc3 can be found in:
|
||||
Documentation/devicetree/bindings/usb/dwc3.txt
|
||||
|
||||
Example:
|
||||
usb@12000000 {
|
||||
compatible = "samsung,exynos5250-dwusb3";
|
||||
clocks = <&clock 286>;
|
||||
clock-names = "usbdrd30";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
dwc3 {
|
||||
compatible = "synopsys,dwc3";
|
||||
reg = <0x12000000 0x10000>;
|
||||
interrupts = <0 72 0>;
|
||||
usb-phy = <&usb2_phy &usb3_phy>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,6 +21,10 @@ Required properties for dp-controller:
|
|||
of memory mapped region.
|
||||
-interrupts:
|
||||
interrupt combiner values.
|
||||
-clocks:
|
||||
from common clock binding: handle to dp clock.
|
||||
-clock-names:
|
||||
from common clock binding: Shall be "dp".
|
||||
-interrupt-parent:
|
||||
phandle to Interrupt combiner node.
|
||||
-samsung,color-space:
|
||||
|
|
@ -61,6 +65,8 @@ SOC specific portion:
|
|||
reg = <0x145b0000 0x10000>;
|
||||
interrupts = <10 3>;
|
||||
interrupt-parent = <&combiner>;
|
||||
clocks = <&clock 342>;
|
||||
clock-names = "dp";
|
||||
|
||||
dptx-phy {
|
||||
reg = <0x10040720>;
|
||||
|
|
|
|||
|
|
@ -16,11 +16,13 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
|
|||
dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
|
||||
# sam9g20
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91-foxg20.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += usb_a9g20_lpw.dtb
|
||||
# sam9g45
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
|
||||
|
|
@ -86,6 +88,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
|
|||
kirkwood-ns2max.dtb \
|
||||
kirkwood-ns2mini.dtb \
|
||||
kirkwood-nsa310.dtb \
|
||||
kirkwood-sheevaplug.dtb \
|
||||
kirkwood-sheevaplug-esata.dtb \
|
||||
kirkwood-topkick.dtb \
|
||||
kirkwood-ts219-6281.dtb \
|
||||
kirkwood-ts219-6282.dtb \
|
||||
|
|
@ -105,13 +109,15 @@ dtb-$(CONFIG_ARCH_MXC) += \
|
|||
imx27-apf27.dtb \
|
||||
imx27-apf27dev.dtb \
|
||||
imx27-pdk.dtb \
|
||||
imx27-phytec-phycore.dtb \
|
||||
imx27-phytec-phycore-som.dtb \
|
||||
imx27-phytec-phycore-rdk.dtb \
|
||||
imx31-bug.dtb \
|
||||
imx51-apf51.dtb \
|
||||
imx51-apf51dev.dtb \
|
||||
imx51-babbage.dtb \
|
||||
imx53-ard.dtb \
|
||||
imx53-evk.dtb \
|
||||
imx53-m53evk.dtb \
|
||||
imx53-mba53.dtb \
|
||||
imx53-qsb.dtb \
|
||||
imx53-smd.dtb \
|
||||
|
|
@ -119,10 +125,13 @@ dtb-$(CONFIG_ARCH_MXC) += \
|
|||
imx6dl-sabresd.dtb \
|
||||
imx6dl-wandboard.dtb \
|
||||
imx6q-arm2.dtb \
|
||||
imx6q-phytec-pbab01.dtb \
|
||||
imx6q-sabreauto.dtb \
|
||||
imx6q-sabrelite.dtb \
|
||||
imx6q-sabresd.dtb \
|
||||
imx6q-sbc6x.dtb
|
||||
imx6q-sbc6x.dtb \
|
||||
imx6sl-evk.dtb \
|
||||
vf610-twr.dtb
|
||||
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
|
||||
imx23-olinuxino.dtb \
|
||||
imx23-stmp378x_devb.dtb \
|
||||
|
|
@ -132,6 +141,8 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
|
|||
imx28-cfa10036.dtb \
|
||||
imx28-cfa10037.dtb \
|
||||
imx28-cfa10049.dtb \
|
||||
imx28-cfa10055.dtb \
|
||||
imx28-cfa10057.dtb \
|
||||
imx28-evk.dtb \
|
||||
imx28-m28evk.dtb \
|
||||
imx28-sps1.dtb \
|
||||
|
|
@ -151,19 +162,26 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
|
|||
omap4-panda-es.dtb \
|
||||
omap4-var-som.dtb \
|
||||
omap4-sdp.dtb \
|
||||
omap5-evm.dtb \
|
||||
omap4-sdp-es23plus.dtb \
|
||||
omap5-uevm.dtb \
|
||||
am335x-evm.dtb \
|
||||
am335x-evmsk.dtb \
|
||||
am335x-bone.dtb
|
||||
am335x-bone.dtb \
|
||||
am3517-evm.dtb \
|
||||
am3517_mt_ventoux.dtb \
|
||||
am43x-epos-evm.dtb
|
||||
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
|
||||
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
|
||||
hrefprev60.dtb \
|
||||
hrefv60plus.dtb \
|
||||
ccu8540.dtb \
|
||||
ccu9540.dtb
|
||||
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
|
||||
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
|
||||
r8a7740-armadillo800eva.dtb \
|
||||
r8a7778-bockw.dtb \
|
||||
r8a7740-armadillo800eva-reference.dtb \
|
||||
r8a7779-marzen-reference.dtb \
|
||||
r8a7790-lager.dtb \
|
||||
sh73a0-kzm9g.dtb \
|
||||
|
|
@ -183,6 +201,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
|
|||
sun4i-a10-cubieboard.dtb \
|
||||
sun4i-a10-mini-xplus.dtb \
|
||||
sun4i-a10-hackberry.dtb \
|
||||
sun5i-a10s-olinuxino-micro.dtb \
|
||||
sun5i-a13-olinuxino.dtb
|
||||
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
|
||||
tegra20-iris-512.dtb \
|
||||
|
|
@ -210,8 +229,11 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb
|
|||
dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
|
||||
wm8505-ref.dtb \
|
||||
wm8650-mid.dtb \
|
||||
wm8750-apc8750.dtb \
|
||||
wm8850-w70v2.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
|
||||
zynq-zc706.dtb \
|
||||
zynq-zed.dtb
|
||||
|
||||
targets += dtbs
|
||||
targets += $(dtb-y)
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "am33xx.dtsi"
|
||||
#include "am33xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM335x BeagleBone";
|
||||
|
|
@ -26,24 +26,104 @@
|
|||
|
||||
am33xx_pinmux: pinmux@44e10800 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&user_leds_s0>;
|
||||
pinctrl-0 = <&clkout2_pin>;
|
||||
|
||||
user_leds_s0: user_leds_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
|
||||
0x58 0x17 /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
|
||||
0x5c 0x7 /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
|
||||
0x60 0x17 /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
|
||||
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
|
||||
0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
|
||||
0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
|
||||
0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
clkout2_pin: pinmux_clkout2_pin {
|
||||
pinctrl-single,pins = <
|
||||
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
|
||||
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
|
||||
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
|
||||
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
|
||||
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
|
||||
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
|
||||
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
|
||||
0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart1: serial@44e09000 {
|
||||
uart0: serial@44e09000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@44e0b000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
|
|
@ -55,31 +135,34 @@
|
|||
};
|
||||
|
||||
leds {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&user_leds_s0>;
|
||||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@2 {
|
||||
label = "beaglebone:green:heartbeat";
|
||||
gpios = <&gpio1 21 0>;
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "beaglebone:green:mmc0";
|
||||
gpios = <&gpio1 22 0>;
|
||||
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
label = "beaglebone:green:usr2";
|
||||
gpios = <&gpio1 23 0>;
|
||||
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@5 {
|
||||
label = "beaglebone:green:usr3";
|
||||
gpios = <&gpio1 24 0>;
|
||||
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
|
@ -136,3 +219,16 @@
|
|||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "am33xx.dtsi"
|
||||
#include "am33xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM335x EVM";
|
||||
|
|
@ -26,32 +26,143 @@
|
|||
|
||||
am33xx_pinmux: pinmux@44e10800 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
|
||||
pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
|
||||
|
||||
matrix_keypad_s0: matrix_keypad_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
|
||||
0x58 0x7 /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */
|
||||
0x64 0x27 /* gpmc_a9.gpio1_25, INPUT | MODE7 */
|
||||
0x68 0x27 /* gpmc_a10.gpio1_26, INPUT | MODE7 */
|
||||
0x6c 0x27 /* gpmc_a11.gpio1_27, INPUT | MODE7 */
|
||||
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
|
||||
0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
|
||||
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
|
||||
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
|
||||
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
|
||||
>;
|
||||
};
|
||||
|
||||
volume_keys_s0: volume_keys_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x150 0x27 /* spi0_sclk.gpio0_2, INPUT | MODE7 */
|
||||
0x154 0x27 /* spi0_d0.gpio0_3, INPUT | MODE7 */
|
||||
0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
|
||||
0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins: pinmux_i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
|
||||
0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
clkout2_pin: pinmux_clkout2_pin {
|
||||
pinctrl-single,pins = <
|
||||
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
|
||||
>;
|
||||
};
|
||||
|
||||
nandflash_pins_s0: nandflash_pins_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
||||
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
||||
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
||||
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
||||
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
||||
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
||||
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
||||
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
||||
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
||||
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
|
||||
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
||||
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
||||
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
||||
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
||||
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
|
||||
ecap0_pins: backlight_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
|
||||
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart1: serial@44e09000 {
|
||||
uart0: serial@44e09000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@44e0b000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
|
|
@ -61,6 +172,9 @@
|
|||
};
|
||||
|
||||
i2c1: i2c@4802a000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
|
|
@ -102,6 +216,101 @@
|
|||
reg = <0x48>;
|
||||
};
|
||||
};
|
||||
|
||||
elm: elm@48080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
epwmss0: epwmss@48300000 {
|
||||
status = "okay";
|
||||
|
||||
ecap0: ecap@48300100 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap0_pins>;
|
||||
};
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nandflash_pins_s0>;
|
||||
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
|
||||
nand@0,0 {
|
||||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
nand-bus-width = <8>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
gpmc,device-nand = "true";
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-on-ns = <0>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
elm_id = <&elm>;
|
||||
|
||||
/* MTD partition table */
|
||||
partition@0 {
|
||||
label = "SPL1";
|
||||
reg = <0x00000000 0x000020000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "SPL2";
|
||||
reg = <0x00020000 0x00020000>;
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "SPL3";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "SPL4";
|
||||
reg = <0x00060000 0x00020000>;
|
||||
};
|
||||
|
||||
partition@4 {
|
||||
label = "U-boot";
|
||||
reg = <0x00080000 0x001e0000>;
|
||||
};
|
||||
|
||||
partition@5 {
|
||||
label = "environment";
|
||||
reg = <0x00260000 0x00020000>;
|
||||
};
|
||||
|
||||
partition@6 {
|
||||
label = "Kernel";
|
||||
reg = <0x00280000 0x00500000>;
|
||||
};
|
||||
|
||||
partition@7 {
|
||||
label = "File-System";
|
||||
reg = <0x00780000 0x0F880000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vbat: fixedregulator@0 {
|
||||
|
|
@ -123,12 +332,12 @@
|
|||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <2>;
|
||||
|
||||
row-gpios = <&gpio1 25 0 /* Bank1, pin25 */
|
||||
&gpio1 26 0 /* Bank1, pin26 */
|
||||
&gpio1 27 0>; /* Bank1, pin27 */
|
||||
row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
|
||||
&gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
|
||||
&gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
|
||||
|
||||
col-gpios = <&gpio1 21 0 /* Bank1, pin21 */
|
||||
&gpio1 22 0>; /* Bank1, pin22 */
|
||||
col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
|
||||
&gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
|
||||
|
||||
linux,keymap = <0x0000008b /* MENU */
|
||||
0x0100009e /* BACK */
|
||||
|
|
@ -147,20 +356,27 @@
|
|||
switch@9 {
|
||||
label = "volume-up";
|
||||
linux,code = <115>;
|
||||
gpios = <&gpio0 2 1>;
|
||||
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
switch@10 {
|
||||
label = "volume-down";
|
||||
linux,code = <114>;
|
||||
gpios = <&gpio0 3 1>;
|
||||
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap0 0 50000 0>;
|
||||
brightness-levels = <0 51 53 56 62 75 101 152 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "tps65910.dtsi"
|
||||
#include "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
|
|
@ -237,6 +453,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "am33xx.dtsi"
|
||||
#include "am33xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM335x EVM-SK";
|
||||
|
|
@ -32,33 +32,145 @@
|
|||
|
||||
am33xx_pinmux: pinmux@44e10800 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>;
|
||||
pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
|
||||
|
||||
user_leds_s0: user_leds_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x10 0x7 /* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */
|
||||
0x14 0x7 /* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */
|
||||
0x18 0x7 /* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */
|
||||
0x1c 0x7 /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */
|
||||
0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
|
||||
0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
|
||||
0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
|
||||
0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
|
||||
>;
|
||||
};
|
||||
|
||||
gpio_keys_s0: gpio_keys_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x94 0x27 /* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */
|
||||
0x90 0x27 /* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */
|
||||
0x70 0x27 /* gpmc_wait0.gpio0_30, INPUT | MODE7 */
|
||||
0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */
|
||||
0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
|
||||
0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
|
||||
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
|
||||
0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
clkout2_pin: pinmux_clkout2_pin {
|
||||
pinctrl-single,pins = <
|
||||
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
|
||||
>;
|
||||
};
|
||||
|
||||
ecap2_pins: backlight_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
|
||||
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
|
||||
|
||||
/* Slave 2 */
|
||||
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
|
||||
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
|
||||
0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
|
||||
0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
|
||||
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
|
||||
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
|
||||
0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
|
||||
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
|
||||
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
|
||||
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
|
||||
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
|
||||
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
|
||||
/* Slave 2 reset value*/
|
||||
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart1: serial@44e09000 {
|
||||
uart0: serial@44e09000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@44e0b000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
|
|
@ -94,6 +206,16 @@
|
|||
st,max-limit-z = <750>;
|
||||
};
|
||||
};
|
||||
|
||||
epwmss2: epwmss@48304000 {
|
||||
status = "okay";
|
||||
|
||||
ecap2: ecap@48304100 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap2_pins>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vbat: fixedregulator@0 {
|
||||
|
|
@ -111,30 +233,33 @@
|
|||
};
|
||||
|
||||
leds {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&user_leds_s0>;
|
||||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@1 {
|
||||
label = "evmsk:green:usr0";
|
||||
gpios = <&gpio1 4 0>;
|
||||
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
label = "evmsk:green:usr1";
|
||||
gpios = <&gpio1 5 0>;
|
||||
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "evmsk:green:mmc0";
|
||||
gpios = <&gpio1 6 0>;
|
||||
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
label = "evmsk:green:heartbeat";
|
||||
gpios = <&gpio1 7 0>;
|
||||
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
|
@ -148,31 +273,38 @@
|
|||
switch@1 {
|
||||
label = "button0";
|
||||
linux,code = <0x100>;
|
||||
gpios = <&gpio2 3 0>;
|
||||
gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
switch@2 {
|
||||
label = "button1";
|
||||
linux,code = <0x101>;
|
||||
gpios = <&gpio2 2 0>;
|
||||
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
switch@3 {
|
||||
label = "button2";
|
||||
linux,code = <0x102>;
|
||||
gpios = <&gpio0 30 0>;
|
||||
gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
switch@4 {
|
||||
label = "button3";
|
||||
linux,code = <0x103>;
|
||||
gpios = <&gpio2 5 0>;
|
||||
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap2 0 50000 1>;
|
||||
brightness-levels = <0 58 61 66 75 90 125 170 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "tps65910.dtsi"
|
||||
#include "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
|
|
@ -248,3 +380,15 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,26 +8,33 @@
|
|||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/am33xx.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am33xx";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
serial5 = &uart6;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &uart5;
|
||||
d_can0 = &dcan0;
|
||||
d_can1 = &dcan1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a8";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
|
||||
/*
|
||||
* To consider voltage drop between PMIC and SoC,
|
||||
|
|
@ -133,7 +140,7 @@
|
|||
interrupts = <62>;
|
||||
};
|
||||
|
||||
uart1: serial@44e09000 {
|
||||
uart0: serial@44e09000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart1";
|
||||
clock-frequency = <48000000>;
|
||||
|
|
@ -142,7 +149,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@48022000 {
|
||||
uart1: serial@48022000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart2";
|
||||
clock-frequency = <48000000>;
|
||||
|
|
@ -151,7 +158,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@48024000 {
|
||||
uart2: serial@48024000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart3";
|
||||
clock-frequency = <48000000>;
|
||||
|
|
@ -160,7 +167,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@481a6000 {
|
||||
uart3: serial@481a6000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
|
|
@ -169,7 +176,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@481a8000 {
|
||||
uart4: serial@481a8000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart5";
|
||||
clock-frequency = <48000000>;
|
||||
|
|
@ -178,7 +185,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@481aa000 {
|
||||
uart5: serial@481aa000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart6";
|
||||
clock-frequency = <48000000>;
|
||||
|
|
@ -343,6 +350,90 @@
|
|||
ti,hwmods = "usb_otg_hs";
|
||||
};
|
||||
|
||||
epwmss0: epwmss@48300000 {
|
||||
compatible = "ti,am33xx-pwmss";
|
||||
reg = <0x48300000 0x10>;
|
||||
ti,hwmods = "epwmss0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
|
||||
0x48300180 0x48300180 0x80 /* EQEP */
|
||||
0x48300200 0x48300200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap0: ecap@48300100 {
|
||||
compatible = "ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300100 0x80>;
|
||||
ti,hwmods = "ecap0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm0: ehrpwm@48300200 {
|
||||
compatible = "ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300200 0x80>;
|
||||
ti,hwmods = "ehrpwm0";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss1: epwmss@48302000 {
|
||||
compatible = "ti,am33xx-pwmss";
|
||||
reg = <0x48302000 0x10>;
|
||||
ti,hwmods = "epwmss1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges = <0x48302100 0x48302100 0x80 /* ECAP */
|
||||
0x48302180 0x48302180 0x80 /* EQEP */
|
||||
0x48302200 0x48302200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap1: ecap@48302100 {
|
||||
compatible = "ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302100 0x80>;
|
||||
ti,hwmods = "ecap1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm1: ehrpwm@48302200 {
|
||||
compatible = "ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302200 0x80>;
|
||||
ti,hwmods = "ehrpwm1";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss2: epwmss@48304000 {
|
||||
compatible = "ti,am33xx-pwmss";
|
||||
reg = <0x48304000 0x10>;
|
||||
ti,hwmods = "epwmss2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges = <0x48304100 0x48304100 0x80 /* ECAP */
|
||||
0x48304180 0x48304180 0x80 /* EQEP */
|
||||
0x48304200 0x48304200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap2: ecap@48304100 {
|
||||
compatible = "ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304100 0x80>;
|
||||
ti,hwmods = "ecap2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm2: ehrpwm@48304200 {
|
||||
compatible = "ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304200 0x80>;
|
||||
ti,hwmods = "ehrpwm2";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
mac: ethernet@4a100000 {
|
||||
compatible = "ti,cpsw";
|
||||
ti,hwmods = "cpgmac0";
|
||||
|
|
@ -403,6 +494,14 @@
|
|||
ti,hwmods = "wkup_m3";
|
||||
};
|
||||
|
||||
elm: elm@48080000 {
|
||||
compatible = "ti,am3352-elm";
|
||||
reg = <0x48080000 0x2000>;
|
||||
interrupts = <4>;
|
||||
ti,hwmods = "elm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap34xx.dtsi"
|
||||
#include "omap34xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM3517 EVM (AM3517/05)";
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap34xx.dtsi"
|
||||
#include "omap34xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TeeJet Mt.Ventoux";
|
||||
|
|
|
|||
68
arch/arm/boot/dts/am4372.dtsi
Normal file
68
arch/arm/boot/dts/am4372.dtsi
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* Device Tree Source for AM4372 SoC
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am4372", "ti,am43";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@48241000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x48241000 0x1000>,
|
||||
<0x48240100 0x0100>;
|
||||
};
|
||||
|
||||
ocp {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
uart0: serial@44e09000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x44e09000 0x2000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer1: timer@44e31000 {
|
||||
compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
|
||||
reg = <0x44e31000 0x400>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-alwon;
|
||||
};
|
||||
|
||||
timer2: timer@48040000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48040000 0x400>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
counter32k: counter@44e86000 {
|
||||
compatible = "ti,am4372-counter32k","ti,omap-counter32k";
|
||||
reg = <0x44e86000 0x40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
18
arch/arm/boot/dts/am43x-epos-evm.dts
Normal file
18
arch/arm/boot/dts/am43x-epos-evm.dts
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* AM43x EPOS EVM */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am4372.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM43x EPOS EVM";
|
||||
compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
|
||||
};
|
||||
|
|
@ -74,6 +74,7 @@
|
|||
*/
|
||||
status = "disabled";
|
||||
/* No CD or WP GPIOs */
|
||||
broken-cd;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
|
|
|
|||
|
|
@ -99,6 +99,7 @@
|
|||
* No CD or WP GPIOs: SDIO interface used for
|
||||
* Wifi/Bluetooth chip
|
||||
*/
|
||||
broken-cd;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@
|
|||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
/* No CD or WP GPIOs */
|
||||
broken-cd;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
|
|
@ -84,6 +85,22 @@
|
|||
gpios = <&gpio0 6 1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -22,9 +22,18 @@
|
|||
model = "Marvell Armada 370 and XP SoC";
|
||||
compatible = "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
eth0 = ð0;
|
||||
eth1 = ð1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
compatible = "marvell,sheeva-v7";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -94,7 +103,7 @@
|
|||
reg = <0x72004 0x4>;
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
eth0: ethernet@70000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts = <8>;
|
||||
|
|
@ -102,7 +111,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@74000 {
|
||||
eth1: ethernet@74000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x74000 0x4000>;
|
||||
interrupts = <10>;
|
||||
|
|
@ -143,6 +152,10 @@
|
|||
reg = <0xd4000 0x200>;
|
||||
interrupts = <54>;
|
||||
clocks = <&gateclk 17>;
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -180,10 +180,6 @@
|
|||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
reg = <0x40000 0x2000>, <0x80000 0x2000>;
|
||||
|
||||
reg-names = "pcie0.0", "pcie1.0";
|
||||
|
||||
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
|
|
|
|||
|
|
@ -30,6 +30,10 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
|
||||
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
|
||||
0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
clock-frequency = <250000000>;
|
||||
|
|
@ -97,6 +101,7 @@
|
|||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
/* No CD or WP GPIOs */
|
||||
broken-cd;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
|
|
@ -155,6 +160,35 @@
|
|||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
devbus-bootcs@10400 {
|
||||
status = "okay";
|
||||
ranges = <0 0xf0000000 0x1000000>;
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <8>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 16 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -105,6 +105,16 @@
|
|||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
/* Front-side USB slot */
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Back-side USB slot */
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
eth3 = ð3;
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -105,7 +106,7 @@
|
|||
interrupts = <91>;
|
||||
};
|
||||
|
||||
ethernet@34000 {
|
||||
eth3: ethernet@34000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x34000 0x4000>;
|
||||
interrupts = <14>;
|
||||
|
|
|
|||
|
|
@ -138,13 +138,22 @@
|
|||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Front side USB 0 */
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Front side USB 1 */
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB interface in the mini-PCIe connector */
|
||||
usb@52000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
devbus-bootcs@10400 {
|
||||
status = "okay";
|
||||
ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,10 @@
|
|||
model = "Marvell Armada XP family SoC";
|
||||
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
eth2 = ð2;
|
||||
};
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
L2: l2-cache {
|
||||
|
|
@ -86,7 +90,7 @@
|
|||
reg = <0x18200 0x500>;
|
||||
};
|
||||
|
||||
ethernet@30000 {
|
||||
eth2: ethernet@30000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x30000 0x4000>;
|
||||
interrupts = <12>;
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
serial3 = &usart2;
|
||||
serial4 = &usart3;
|
||||
serial5 = &uart0;
|
||||
serial6 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -112,13 +113,17 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* UART0/1 pins are marked as GPIO on
|
||||
* Aria documentation.
|
||||
* Change to "okay" if you need additional serial ports
|
||||
*/
|
||||
uart0: serial@f8040000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8040000 0x200>;
|
||||
interrupts = <15 4 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@f8044000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc0: adc@f804c000 {
|
||||
|
|
@ -138,6 +143,10 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
rtc@fffffeb0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00600000 {
|
||||
|
|
|
|||
157
arch/arm/boot/dts/at91-foxg20.dts
Normal file
157
arch/arm/boot/dts/at91-foxg20.dts
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board
|
||||
*
|
||||
* Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC)
|
||||
*
|
||||
* Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9g20.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Acme Systems FoxG20";
|
||||
compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
usb1: gadget@fffa4000 {
|
||||
atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: mmc@fffa8000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_mmc0_clk
|
||||
&pinctrl_mmc0_slot1_cmd_dat0
|
||||
&pinctrl_mmc0_slot1_dat1_3>;
|
||||
status = "okay";
|
||||
|
||||
slot@1 {
|
||||
reg = <1>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
usart0: serial@fffb0000 {
|
||||
pinctrl-0 =
|
||||
<&pinctrl_usart0
|
||||
&pinctrl_usart0_rts
|
||||
&pinctrl_usart0_cts
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@fffb4000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart2: serial@fffb8000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffc4000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart3: serial@fffd0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart0: serial@fffd4000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart1: serial@fffd8000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
board {
|
||||
pinctrl_pck0_as_mck: pck0_as_mck {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_slot1 {
|
||||
pinctrl_board_mmc0_slot1: mmc0_slot1-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* CD pin */
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
pinctrl_i2c0: i2c0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* TWD (SDA), open drain */
|
||||
AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* TWCK (SCL), open drain */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
num-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
i2c-gpio,delay-us = <5>; /* ~85 kHz */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
/* red LED marked "PC7" near mini USB (device) receptacle */
|
||||
user_led {
|
||||
label = "user_led";
|
||||
gpios = <&pioC 7 GPIO_ACTIVE_HIGH>; /* PC7 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
btn {
|
||||
label = "Button";
|
||||
gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <0x103>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -38,8 +38,12 @@
|
|||
ssc2 = &ssc2;
|
||||
};
|
||||
cpus {
|
||||
cpu@0 {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm920t";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -398,6 +402,91 @@
|
|||
};
|
||||
};
|
||||
|
||||
tcb0 {
|
||||
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
tcb1 {
|
||||
pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0 {
|
||||
pinctrl_spi0: spi0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
|
||||
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
|
||||
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
|
|
@ -498,6 +587,17 @@
|
|||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@fffe0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xfffe0000 0x200>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
|
|
|
|||
|
|
@ -53,6 +53,16 @@
|
|||
atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@fffe0000 {
|
||||
status = "okay";
|
||||
cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
|
||||
mtd_dataflash@0 {
|
||||
compatible = "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <15000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00300000 {
|
||||
|
|
|
|||
|
|
@ -35,8 +35,12 @@
|
|||
ssc0 = &ssc0;
|
||||
};
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ejs";
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -347,6 +351,90 @@
|
|||
};
|
||||
};
|
||||
|
||||
i2c_gpio0 {
|
||||
pinctrl_i2c_gpio0: i2c_gpio0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE
|
||||
AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
|
||||
};
|
||||
};
|
||||
|
||||
tcb0 {
|
||||
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
tcb1 {
|
||||
pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
|
|
@ -599,6 +687,8 @@
|
|||
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c_gpio0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -32,8 +32,12 @@
|
|||
ssc1 = &ssc1;
|
||||
};
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ejs";
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -324,6 +328,44 @@
|
|||
};
|
||||
};
|
||||
|
||||
tcb0 {
|
||||
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff200 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff200 0x200>;
|
||||
|
|
|
|||
|
|
@ -89,6 +89,10 @@
|
|||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
|
|
|
|||
|
|
@ -104,6 +104,10 @@
|
|||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/dma/at91.h>
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
@ -38,8 +39,12 @@
|
|||
ssc1 = &ssc1;
|
||||
};
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ejs";
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -344,6 +349,82 @@
|
|||
};
|
||||
};
|
||||
|
||||
tcb0 {
|
||||
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
tcb1 {
|
||||
pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff200 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff200 0x200>;
|
||||
|
|
@ -537,7 +618,7 @@
|
|||
compatible = "atmel,hsmci";
|
||||
reg = <0xfff80000 0x600>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dmas = <&dma 1 0>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
|
||||
dma-names = "rxtx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -548,7 +629,7 @@
|
|||
compatible = "atmel,hsmci";
|
||||
reg = <0xfffd0000 0x600>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dmas = <&dma 1 13>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
|
||||
dma-names = "rxtx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -582,6 +663,68 @@
|
|||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2: gadget@fff78000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,at91sam9rl-udc";
|
||||
reg = <0x00600000 0x80000
|
||||
0xfff78000 0x400>;
|
||||
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
status = "disabled";
|
||||
|
||||
ep0 {
|
||||
reg = <0>;
|
||||
atmel,fifo-size = <64>;
|
||||
atmel,nb-banks = <1>;
|
||||
};
|
||||
|
||||
ep1 {
|
||||
reg = <1>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <2>;
|
||||
atmel,can-dma;
|
||||
atmel,can-isoc;
|
||||
};
|
||||
|
||||
ep2 {
|
||||
reg = <2>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <2>;
|
||||
atmel,can-dma;
|
||||
atmel,can-isoc;
|
||||
};
|
||||
|
||||
ep3 {
|
||||
reg = <3>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <3>;
|
||||
atmel,can-dma;
|
||||
};
|
||||
|
||||
ep4 {
|
||||
reg = <4>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <3>;
|
||||
atmel,can-dma;
|
||||
};
|
||||
|
||||
ep5 {
|
||||
reg = <5>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <3>;
|
||||
atmel,can-dma;
|
||||
atmel,can-isoc;
|
||||
};
|
||||
|
||||
ep6 {
|
||||
reg = <6>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <3>;
|
||||
atmel,can-dma;
|
||||
atmel,can-isoc;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
|
|
|
|||
|
|
@ -59,6 +59,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: mmc@fff80000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_board_mmc0
|
||||
|
|
@ -112,6 +116,11 @@
|
|||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2: gadget@fff78000 {
|
||||
atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/dma/at91.h>
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
@ -34,8 +35,12 @@
|
|||
ssc0 = &ssc0;
|
||||
};
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ejs";
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -93,7 +98,7 @@
|
|||
compatible = "atmel,hsmci";
|
||||
reg = <0xf0008000 0x600>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dmas = <&dma 1 0>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
|
||||
dma-names = "rxtx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -286,6 +291,82 @@
|
|||
};
|
||||
};
|
||||
|
||||
tcb0 {
|
||||
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
tcb1 {
|
||||
pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
|
|
@ -385,8 +466,8 @@
|
|||
compatible = "atmel,at91sam9x5-i2c";
|
||||
reg = <0xf8010000 0x100>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
dmas = <&dma 1 13>,
|
||||
<&dma 1 14>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
|
||||
<&dma 1 AT91_DMA_CFG_PER_ID(14)>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -397,8 +478,8 @@
|
|||
compatible = "atmel,at91sam9x5-i2c";
|
||||
reg = <0xf8014000 0x100>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
dmas = <&dma 1 15>,
|
||||
<&dma 1 16>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
|
||||
<&dma 1 AT91_DMA_CFG_PER_ID(16)>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -411,6 +492,9 @@
|
|||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xf0000000 0x100>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
|
||||
<&dma 1 AT91_DMA_CFG_PER_ID(2)>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
status = "disabled";
|
||||
|
|
@ -422,10 +506,19 @@
|
|||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xf0004000 0x100>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
|
||||
<&dma 1 AT91_DMA_CFG_PER_ID(4)>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog@fffffe40 {
|
||||
compatible = "atmel,at91sam9260-wdt";
|
||||
reg = <0xfffffe40 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
|
|
|
|||
|
|
@ -77,6 +77,10 @@
|
|||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffe40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/dma/at91.h>
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
@ -36,8 +37,12 @@
|
|||
ssc0 = &ssc0;
|
||||
};
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ejs";
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -414,6 +419,82 @@
|
|||
};
|
||||
};
|
||||
|
||||
tcb0 {
|
||||
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
tcb1 {
|
||||
pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
|
|
@ -470,7 +551,7 @@
|
|||
compatible = "atmel,hsmci";
|
||||
reg = <0xf0008000 0x600>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dmas = <&dma0 1 0>;
|
||||
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
|
||||
dma-names = "rxtx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -481,7 +562,7 @@
|
|||
compatible = "atmel,hsmci";
|
||||
reg = <0xf000c000 0x600>;
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dmas = <&dma1 1 0>;
|
||||
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
|
||||
dma-names = "rxtx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -544,8 +625,8 @@
|
|||
compatible = "atmel,at91sam9x5-i2c";
|
||||
reg = <0xf8010000 0x100>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
dmas = <&dma0 1 7>,
|
||||
<&dma0 1 8>;
|
||||
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
|
||||
<&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -558,8 +639,8 @@
|
|||
compatible = "atmel,at91sam9x5-i2c";
|
||||
reg = <0xf8014000 0x100>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
dmas = <&dma1 1 5>,
|
||||
<&dma1 1 6>;
|
||||
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
|
||||
<&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -572,8 +653,8 @@
|
|||
compatible = "atmel,at91sam9x5-i2c";
|
||||
reg = <0xf8018000 0x100>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
dmas = <&dma0 1 9>,
|
||||
<&dma0 1 10>;
|
||||
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
|
||||
<&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -582,6 +663,24 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@f8040000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8040000 0x200>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@f8044000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8044000 0x200>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc0: adc@f804c000 {
|
||||
compatible = "atmel,at91sam9260-adc";
|
||||
reg = <0xf804c000 0x100>;
|
||||
|
|
@ -629,6 +728,9 @@
|
|||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xf0000000 0x100>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
|
||||
<&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
status = "disabled";
|
||||
|
|
@ -640,13 +742,84 @@
|
|||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xf0004000 0x100>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
|
||||
<&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2: gadget@f803c000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,at91sam9rl-udc";
|
||||
reg = <0x00500000 0x80000
|
||||
0xf803c000 0x400>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
status = "disabled";
|
||||
|
||||
ep0 {
|
||||
reg = <0>;
|
||||
atmel,fifo-size = <64>;
|
||||
atmel,nb-banks = <1>;
|
||||
};
|
||||
|
||||
ep1 {
|
||||
reg = <1>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <2>;
|
||||
atmel,can-dma;
|
||||
atmel,can-isoc;
|
||||
};
|
||||
|
||||
ep2 {
|
||||
reg = <2>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <2>;
|
||||
atmel,can-dma;
|
||||
atmel,can-isoc;
|
||||
};
|
||||
|
||||
ep3 {
|
||||
reg = <3>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <3>;
|
||||
atmel,can-dma;
|
||||
};
|
||||
|
||||
ep4 {
|
||||
reg = <4>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <3>;
|
||||
atmel,can-dma;
|
||||
};
|
||||
|
||||
ep5 {
|
||||
reg = <5>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <3>;
|
||||
atmel,can-dma;
|
||||
atmel,can-isoc;
|
||||
};
|
||||
|
||||
ep6 {
|
||||
reg = <6>;
|
||||
atmel,fifo-size = <1024>;
|
||||
atmel,nb-banks = <3>;
|
||||
atmel,can-dma;
|
||||
atmel,can-isoc;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffe40 {
|
||||
compatible = "atmel,at91sam9260-wdt";
|
||||
reg = <0xfffffe40 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@fffffeb0 {
|
||||
compatible = "atmel,at91rm9200-rtc";
|
||||
compatible = "atmel,at91sam9x5-rtc";
|
||||
reg = <0xfffffeb0 0x40>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -52,6 +52,11 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
usb2: gadget@f803c000 {
|
||||
atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@f8010000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -81,6 +86,10 @@
|
|||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffe40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00600000 {
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "bcm11351.dtsi"
|
||||
#include "bcm11351.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BCM11351 BRT board";
|
||||
|
|
@ -27,4 +27,21 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
sdio0: sdio@0x3f180000 {
|
||||
max-frequency = <48000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdio1: sdio@0x3f190000 {
|
||||
non-removable;
|
||||
max-frequency = <48000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdio3: sdio@0x3f1b0000 {
|
||||
max-frequency = <48000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,7 +11,10 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BCM11351 SoC";
|
||||
|
|
@ -33,7 +36,7 @@
|
|||
|
||||
smc@0x3404c000 {
|
||||
compatible = "bcm,bcm11351-smc", "bcm,kona-smc";
|
||||
reg = <0x3404c000 0x400>; //1 KiB in SRAM
|
||||
reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
|
||||
};
|
||||
|
||||
uart@3e000000 {
|
||||
|
|
@ -41,7 +44,7 @@
|
|||
status = "disabled";
|
||||
reg = <0x3e000000 0x1000>;
|
||||
clock-frequency = <13000000>;
|
||||
interrupts = <0x0 67 0x4>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
|
@ -56,8 +59,36 @@
|
|||
timer@35006000 {
|
||||
compatible = "bcm,kona-timer";
|
||||
reg = <0x35006000 0x1000>;
|
||||
interrupts = <0x0 7 0x4>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
sdio0: sdio@0x3f180000 {
|
||||
compatible = "bcm,kona-sdhci";
|
||||
reg = <0x3f180000 0x10000>;
|
||||
interrupts = <0x0 77 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio1: sdio@0x3f190000 {
|
||||
compatible = "bcm,kona-sdhci";
|
||||
reg = <0x3f190000 0x10000>;
|
||||
interrupts = <0x0 76 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio2: sdio@0x3f1a0000 {
|
||||
compatible = "bcm,kona-sdhci";
|
||||
reg = <0x3f1a0000 0x10000>;
|
||||
interrupts = <0x0 74 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio3: sdio@0x3f1b0000 {
|
||||
compatible = "bcm,kona-sdhci";
|
||||
reg = <0x3f1b0000 0x10000>;
|
||||
interrupts = <0x0 73 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,6 +8,17 @@
|
|||
memory {
|
||||
reg = <0 0x10000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
act {
|
||||
label = "ACT";
|
||||
gpios = <&gpio 16 1>;
|
||||
default-state = "keep";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
|
|
|
|||
41
arch/arm/boot/dts/ccu8540.dts
Normal file
41
arch/arm/boot/dts/ccu8540.dts
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright 2013 ST-Ericsson AB
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "dbx5x0.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ST-Ericsson U8540 platform with Device Tree";
|
||||
compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
prcmu@80157000 {
|
||||
reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>;
|
||||
reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
|
||||
};
|
||||
|
||||
uart@80120000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart@80121000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart@80007000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "dbx5x0.dtsi"
|
||||
#include "dbx5x0.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ST-Ericsson CCU9540 platform with Device Tree";
|
||||
|
|
@ -20,7 +20,7 @@
|
|||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
soc-u9500 {
|
||||
soc {
|
||||
uart@80120000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -52,7 +52,7 @@
|
|||
// WLAN SDIO channel
|
||||
sdi1_per2@80118000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
max-frequency = <50000000>;
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <4>;
|
||||
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -9,10 +9,11 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
soc-u9500 {
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "stericsson,db8500";
|
||||
|
|
@ -31,33 +32,33 @@
|
|||
L2: l2-cache {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xa0412000 0x1000>;
|
||||
interrupts = <0 13 4>;
|
||||
interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 7 0x4>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer@a0410600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xa0410600 0x20>;
|
||||
interrupts = <1 13 0x304>;
|
||||
interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
|
||||
};
|
||||
|
||||
rtc@80154000 {
|
||||
compatible = "arm,rtc-pl031", "arm,primecell";
|
||||
reg = <0x80154000 0x1000>;
|
||||
interrupts = <0 18 0x4>;
|
||||
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio0: gpio@8012e000 {
|
||||
compatible = "stericsson,db8500-gpio",
|
||||
"st,nomadik-gpio";
|
||||
reg = <0x8012e000 0x80>;
|
||||
interrupts = <0 119 0x4>;
|
||||
interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
st,supports-sleepmode;
|
||||
|
|
@ -70,7 +71,7 @@
|
|||
compatible = "stericsson,db8500-gpio",
|
||||
"st,nomadik-gpio";
|
||||
reg = <0x8012e080 0x80>;
|
||||
interrupts = <0 120 0x4>;
|
||||
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
st,supports-sleepmode;
|
||||
|
|
@ -83,7 +84,7 @@
|
|||
compatible = "stericsson,db8500-gpio",
|
||||
"st,nomadik-gpio";
|
||||
reg = <0x8000e000 0x80>;
|
||||
interrupts = <0 121 0x4>;
|
||||
interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
st,supports-sleepmode;
|
||||
|
|
@ -96,7 +97,7 @@
|
|||
compatible = "stericsson,db8500-gpio",
|
||||
"st,nomadik-gpio";
|
||||
reg = <0x8000e080 0x80>;
|
||||
interrupts = <0 122 0x4>;
|
||||
interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
st,supports-sleepmode;
|
||||
|
|
@ -109,7 +110,7 @@
|
|||
compatible = "stericsson,db8500-gpio",
|
||||
"st,nomadik-gpio";
|
||||
reg = <0x8000e100 0x80>;
|
||||
interrupts = <0 123 0x4>;
|
||||
interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
st,supports-sleepmode;
|
||||
|
|
@ -122,7 +123,7 @@
|
|||
compatible = "stericsson,db8500-gpio",
|
||||
"st,nomadik-gpio";
|
||||
reg = <0x8000e180 0x80>;
|
||||
interrupts = <0 124 0x4>;
|
||||
interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
st,supports-sleepmode;
|
||||
|
|
@ -135,7 +136,7 @@
|
|||
compatible = "stericsson,db8500-gpio",
|
||||
"st,nomadik-gpio";
|
||||
reg = <0x8011e000 0x80>;
|
||||
interrupts = <0 125 0x4>;
|
||||
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
st,supports-sleepmode;
|
||||
|
|
@ -148,7 +149,7 @@
|
|||
compatible = "stericsson,db8500-gpio",
|
||||
"st,nomadik-gpio";
|
||||
reg = <0x8011e080 0x80>;
|
||||
interrupts = <0 126 0x4>;
|
||||
interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
st,supports-sleepmode;
|
||||
|
|
@ -161,7 +162,7 @@
|
|||
compatible = "stericsson,db8500-gpio",
|
||||
"st,nomadik-gpio";
|
||||
reg = <0xa03fe000 0x80>;
|
||||
interrupts = <0 127 0x4>;
|
||||
interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
st,supports-sleepmode;
|
||||
|
|
@ -171,29 +172,61 @@
|
|||
};
|
||||
|
||||
pinctrl {
|
||||
compatible = "stericsson,nmk-pinctrl";
|
||||
compatible = "stericsson,db8500-pinctrl";
|
||||
prcm = <&prcmu>;
|
||||
};
|
||||
|
||||
usb@a03e0000 {
|
||||
usb_per5@a03e0000 {
|
||||
compatible = "stericsson,db8500-musb",
|
||||
"mentor,musb";
|
||||
reg = <0xa03e0000 0x10000>;
|
||||
interrupts = <0 23 0x4>;
|
||||
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mc";
|
||||
|
||||
dr_mode = "otg";
|
||||
|
||||
dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 38 0 0x0>, /* Logical - MemToDev */
|
||||
<&dma 37 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 37 0 0x0>, /* Logical - MemToDev */
|
||||
<&dma 36 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 36 0 0x0>, /* Logical - MemToDev */
|
||||
<&dma 19 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 19 0 0x0>, /* Logical - MemToDev */
|
||||
<&dma 18 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 18 0 0x0>, /* Logical - MemToDev */
|
||||
<&dma 17 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 17 0 0x0>, /* Logical - MemToDev */
|
||||
<&dma 16 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 16 0 0x0>, /* Logical - MemToDev */
|
||||
<&dma 39 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 39 0 0x0>; /* Logical - MemToDev */
|
||||
|
||||
dma-names = "iep_1_9", "oep_1_9",
|
||||
"iep_2_10", "oep_2_10",
|
||||
"iep_3_11", "oep_3_11",
|
||||
"iep_4_12", "oep_4_12",
|
||||
"iep_5_13", "oep_5_13",
|
||||
"iep_6_14", "oep_6_14",
|
||||
"iep_7_15", "oep_7_15",
|
||||
"iep_8", "oep_8";
|
||||
};
|
||||
|
||||
dma-controller@801C0000 {
|
||||
compatible = "stericsson,db8500-dma40",
|
||||
"stericsson,dma40";
|
||||
dma: dma-controller@801C0000 {
|
||||
compatible = "stericsson,db8500-dma40", "stericsson,dma40";
|
||||
reg = <0x801C0000 0x1000 0x40010000 0x800>;
|
||||
interrupts = <0 25 0x4>;
|
||||
reg-names = "base", "lcpa";
|
||||
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#dma-cells = <3>;
|
||||
memcpy-channels = <56 57 58 59 60>;
|
||||
};
|
||||
|
||||
prcmu: prcmu@80157000 {
|
||||
compatible = "stericsson,db8500-prcmu";
|
||||
reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
|
||||
reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
|
||||
interrupts = <0 47 0x4>;
|
||||
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
|
|
@ -208,7 +241,8 @@
|
|||
thermal@801573c0 {
|
||||
compatible = "stericsson,db8500-thermal";
|
||||
reg = <0x801573c0 0x40>;
|
||||
interrupts = <21 0x4>, <22 0x4>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -322,21 +356,21 @@
|
|||
ab8500 {
|
||||
compatible = "stericsson,ab8500";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 40 0x4>;
|
||||
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
ab8500-rtc {
|
||||
compatible = "stericsson,ab8500-rtc";
|
||||
interrupts = <17 0x4
|
||||
18 0x4>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH
|
||||
18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "60S", "ALARM";
|
||||
};
|
||||
|
||||
ab8500-gpadc {
|
||||
compatible = "stericsson,ab8500-gpadc";
|
||||
interrupts = <32 0x4
|
||||
39 0x4>;
|
||||
interrupts = <32 IRQ_TYPE_LEVEL_HIGH
|
||||
39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "HW_CONV_END", "SW_CONV_END";
|
||||
vddadc-supply = <&ab8500_ldo_tvout_reg>;
|
||||
};
|
||||
|
|
@ -369,13 +403,13 @@
|
|||
|
||||
ab8500_usb {
|
||||
compatible = "stericsson,ab8500-usb";
|
||||
interrupts = < 90 0x4
|
||||
96 0x4
|
||||
14 0x4
|
||||
15 0x4
|
||||
79 0x4
|
||||
74 0x4
|
||||
75 0x4>;
|
||||
interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
|
||||
96 IRQ_TYPE_LEVEL_HIGH
|
||||
14 IRQ_TYPE_LEVEL_HIGH
|
||||
15 IRQ_TYPE_LEVEL_HIGH
|
||||
79 IRQ_TYPE_LEVEL_HIGH
|
||||
74 IRQ_TYPE_LEVEL_HIGH
|
||||
75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ID_WAKEUP_R",
|
||||
"ID_WAKEUP_F",
|
||||
"VBUS_DET_F",
|
||||
|
|
@ -383,15 +417,15 @@
|
|||
"USB_LINK_STATUS",
|
||||
"USB_ADP_PROBE_PLUG",
|
||||
"USB_ADP_PROBE_UNPLUG";
|
||||
vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
|
||||
vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
|
||||
v-ape-supply = <&db8500_vape_reg>;
|
||||
musb_1v8-supply = <&db8500_vsmps2_reg>;
|
||||
};
|
||||
|
||||
ab8500-ponkey {
|
||||
compatible = "stericsson,ab8500-poweron-key";
|
||||
interrupts = <6 0x4
|
||||
7 0x4>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_HIGH
|
||||
7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
|
||||
};
|
||||
|
||||
|
|
@ -410,6 +444,11 @@
|
|||
codec: ab8500-codec {
|
||||
compatible = "stericsson,ab8500-codec";
|
||||
|
||||
V-AUD-supply = <&ab8500_ldo_audio_reg>;
|
||||
V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
|
||||
V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
|
||||
V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
|
||||
|
||||
stericsson,earpeice-cmv = <950>; /* Units in mV. */
|
||||
};
|
||||
|
||||
|
|
@ -441,8 +480,8 @@
|
|||
};
|
||||
|
||||
// supply for v-intcore12; VINTCORE12 LDO
|
||||
ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
|
||||
regulator-compatible = "ab8500_ldo_initcore";
|
||||
ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
|
||||
regulator-compatible = "ab8500_ldo_intcore";
|
||||
};
|
||||
|
||||
// supply for tvout; gpadc; TVOUT LDO
|
||||
|
|
@ -460,14 +499,14 @@
|
|||
regulator-compatible = "ab8500_ldo_audio";
|
||||
};
|
||||
|
||||
// supply for v-anamic1 VAMic1-LDO
|
||||
// supply for v-anamic1 VAMIC1 LDO
|
||||
ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
|
||||
regulator-compatible = "ab8500_ldo_anamic1";
|
||||
};
|
||||
|
||||
// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
|
||||
ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
|
||||
regulator-compatible = "ab8500_ldo_amamic2";
|
||||
ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
|
||||
regulator-compatible = "ab8500_ldo_anamic2";
|
||||
};
|
||||
|
||||
// supply for v-dmic; VDMIC LDO
|
||||
|
|
@ -486,7 +525,7 @@
|
|||
i2c@80004000 {
|
||||
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
|
||||
reg = <0x80004000 0x1000>;
|
||||
interrupts = <0 21 0x4>;
|
||||
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,primecell-periphid = <0x180024>;
|
||||
|
||||
#address-cells = <1>;
|
||||
|
|
@ -499,7 +538,7 @@
|
|||
i2c@80122000 {
|
||||
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
|
||||
reg = <0x80122000 0x1000>;
|
||||
interrupts = <0 22 0x4>;
|
||||
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,primecell-periphid = <0x180024>;
|
||||
|
||||
#address-cells = <1>;
|
||||
|
|
@ -512,7 +551,7 @@
|
|||
i2c@80128000 {
|
||||
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
|
||||
reg = <0x80128000 0x1000>;
|
||||
interrupts = <0 55 0x4>;
|
||||
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,primecell-periphid = <0x180024>;
|
||||
|
||||
#address-cells = <1>;
|
||||
|
|
@ -525,7 +564,7 @@
|
|||
i2c@80110000 {
|
||||
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
|
||||
reg = <0x80110000 0x1000>;
|
||||
interrupts = <0 12 0x4>;
|
||||
interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,primecell-periphid = <0x180024>;
|
||||
|
||||
#address-cells = <1>;
|
||||
|
|
@ -538,7 +577,7 @@
|
|||
i2c@8012a000 {
|
||||
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
|
||||
reg = <0x8012a000 0x1000>;
|
||||
interrupts = <0 51 0x4>;
|
||||
interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,primecell-periphid = <0x180024>;
|
||||
|
||||
#address-cells = <1>;
|
||||
|
|
@ -551,82 +590,114 @@
|
|||
ssp@80002000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x80002000 0x1000>;
|
||||
interrupts = <0 14 0x4>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
// Add one of these for each child device
|
||||
cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4
|
||||
&gpio6 22 0x4 &gpio7 0 0x4>;
|
||||
|
||||
};
|
||||
|
||||
uart@80120000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x80120000 0x1000>;
|
||||
interrupts = <0 11 0x4>;
|
||||
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 13 0 0x0>; /* Logical - MemToDev */
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart@80121000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x80121000 0x1000>;
|
||||
interrupts = <0 19 0x4>;
|
||||
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 12 0 0x0>; /* Logical - MemToDev */
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart@80007000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x80007000 0x1000>;
|
||||
interrupts = <0 26 0x4>;
|
||||
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 11 0 0x0>; /* Logical - MemToDev */
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdi0_per1@80126000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x80126000 0x1000>;
|
||||
interrupts = <0 60 0x4>;
|
||||
interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 29 0 0x0>; /* Logical - MemToDev */
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdi1_per2@80118000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x80118000 0x1000>;
|
||||
interrupts = <0 50 0x4>;
|
||||
interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 32 0 0x0>; /* Logical - MemToDev */
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdi2_per3@80005000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x80005000 0x1000>;
|
||||
interrupts = <0 41 0x4>;
|
||||
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 28 0 0x0>; /* Logical - MemToDev */
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdi3_per2@80119000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x80119000 0x1000>;
|
||||
interrupts = <0 59 0x4>;
|
||||
interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdi4_per2@80114000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x80114000 0x1000>;
|
||||
interrupts = <0 99 0x4>;
|
||||
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
|
||||
<&dma 42 0 0x0>; /* Logical - MemToDev */
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdi5_per3@80008000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x80008000 0x1000>;
|
||||
interrupts = <0 100 0x4>;
|
||||
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msp0: msp@80123000 {
|
||||
compatible = "stericsson,ux500-msp-i2s";
|
||||
reg = <0x80123000 0x1000>;
|
||||
interrupts = <0 31 0x4>;
|
||||
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
v-ape-supply = <&db8500_vape_reg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -634,7 +705,7 @@
|
|||
msp1: msp@80124000 {
|
||||
compatible = "stericsson,ux500-msp-i2s";
|
||||
reg = <0x80124000 0x1000>;
|
||||
interrupts = <0 62 0x4>;
|
||||
interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
v-ape-supply = <&db8500_vape_reg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -643,7 +714,7 @@
|
|||
msp2: msp@80117000 {
|
||||
compatible = "stericsson,ux500-msp-i2s";
|
||||
reg = <0x80117000 0x1000>;
|
||||
interrupts = <0 98 0x4>;
|
||||
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
v-ape-supply = <&db8500_vape_reg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -651,7 +722,7 @@
|
|||
msp3: msp@80125000 {
|
||||
compatible = "stericsson,ux500-msp-i2s";
|
||||
reg = <0x80125000 0x1000>;
|
||||
interrupts = <0 62 0x4>;
|
||||
interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
v-ape-supply = <&db8500_vape_reg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -686,5 +757,20 @@
|
|||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cryp@a03cb000 {
|
||||
compatible = "stericsson,ux500-cryp";
|
||||
reg = <0xa03cb000 0x1000>;
|
||||
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
v-ape-supply = <&db8500_vape_reg>;
|
||||
};
|
||||
|
||||
hash@a03c2000 {
|
||||
compatible = "stericsson,ux500-hash";
|
||||
reg = <0xa03c2000 0x1000>;
|
||||
|
||||
v-ape-supply = <&db8500_vape_reg>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -44,11 +44,60 @@
|
|||
gpio = <&gpio0 1 0>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 25MHz reference crystal */
|
||||
ref25: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 { status = "okay"; };
|
||||
&sata0 { status = "okay"; };
|
||||
&i2c0 { status = "okay"; };
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
si5351: clock-generator {
|
||||
compatible = "silabs,si5351a-msop";
|
||||
reg = <0x60>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
/* connect xtal input to 25MHz reference */
|
||||
clocks = <&ref25>;
|
||||
|
||||
/* connect xtal input as source of pll0 and pll1 */
|
||||
silabs,pll-source = <0 0>, <1 0>;
|
||||
|
||||
clkout0 {
|
||||
reg = <0>;
|
||||
silabs,drive-strength = <8>;
|
||||
silabs,multisynth-source = <0>;
|
||||
silabs,clock-source = <0>;
|
||||
silabs,pll-master;
|
||||
};
|
||||
|
||||
clkout1 {
|
||||
reg = <1>;
|
||||
silabs,drive-strength = <8>;
|
||||
silabs,multisynth-source = <1>;
|
||||
silabs,clock-source = <0>;
|
||||
silabs,pll-master;
|
||||
};
|
||||
|
||||
clkout2 {
|
||||
reg = <2>;
|
||||
silabs,multisynth-source = <1>;
|
||||
silabs,clock-source = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -160,6 +160,8 @@
|
|||
reg = <0x13400000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
clocks = <&clock 170>, <&clock 273>;
|
||||
clock-names = "sclk_mfc", "mfc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -41,6 +41,10 @@
|
|||
enable-active-high;
|
||||
};
|
||||
|
||||
tmu@100C0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
|
||||
|
|
@ -83,6 +87,150 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@13860000 {
|
||||
status = "okay";
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <20000>;
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
max8997_pmic@66 {
|
||||
compatible = "maxim,max8997-pmic";
|
||||
reg = <0x66>;
|
||||
interrupt-parent = <&gpx0>;
|
||||
interrupts = <4 0>, <3 0>;
|
||||
|
||||
max8997,pmic-buck1-dvs-voltage = <1350000>;
|
||||
max8997,pmic-buck2-dvs-voltage = <1100000>;
|
||||
max8997,pmic-buck5-dvs-voltage = <1200000>;
|
||||
|
||||
regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "VDD_ABB_3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "VDD_ALIVE_1.1V";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "VMIPI_1.1V";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "VDD_RTC_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "VMIPI_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "VDD_AUD_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
regulator-name = "VADC_3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo9_reg: LDO9 {
|
||||
regulator-name = "DVDD_SWB_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "VDD_PLL_1.1V";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo11_reg: LDO11 {
|
||||
regulator-name = "VDD_AUD_3V";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "AVDD18_SWB_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo17_reg: LDO17 {
|
||||
regulator-name = "VDD_SWB_3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo21_reg: LDO21 {
|
||||
regulator-name = "VDD_MIF_1.2V";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "VDD_ARM_1.2V";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "VDD_INT_1.1V";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "VDD_G3D_1.1V";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "VDDQ_M1M2_1.2V";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck7_reg: BUCK7 {
|
||||
regulator-name = "VDD_LCD_3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -143,4 +291,25 @@
|
|||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
fimd@11c00000 {
|
||||
pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing {
|
||||
clock-frequency = <50000>;
|
||||
hactive = <1024>;
|
||||
vactive = <600>;
|
||||
hfront-porch = <64>;
|
||||
hback-porch = <16>;
|
||||
hsync-len = <48>;
|
||||
vback-porch = <64>;
|
||||
vfront-porch = <16>;
|
||||
vsync-len = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -330,6 +330,95 @@
|
|||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
pwm0_out: pwm0-out {
|
||||
samsung,pins = "gpd0-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
pwm1_out: pwm1-out {
|
||||
samsung,pins = "gpd0-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
pwm2_out: pwm2-out {
|
||||
samsung,pins = "gpd0-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
pwm3_out: pwm3-out {
|
||||
samsung,pins = "gpd0-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
lcd_ctrl: lcd-ctrl {
|
||||
samsung,pins = "gpd0-0", "gpd0-1";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
lcd_sync: lcd-sync {
|
||||
samsung,pins = "gpf0-0", "gpf0-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
lcd_en: lcd-en {
|
||||
samsung,pins = "gpe3-4";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
lcd_clk: lcd-clk {
|
||||
samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
lcd_data16: lcd-data-width16 {
|
||||
samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
|
||||
"gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
|
||||
"gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
|
||||
"gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
lcd_data18: lcd-data-width18 {
|
||||
samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
|
||||
"gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
|
||||
"gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
|
||||
"gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
|
||||
"gpf3-2", "gpf3-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
lcd_data24: lcd-data-width24 {
|
||||
samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
|
||||
"gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
|
||||
"gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
|
||||
"gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
|
||||
"gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
|
||||
"gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@11000000 {
|
||||
|
|
|
|||
|
|
@ -112,12 +112,17 @@
|
|||
interrupt-parent = <&combiner>;
|
||||
reg = <0x100C0000 0x100>;
|
||||
interrupts = <2 4>;
|
||||
clocks = <&clock 383>;
|
||||
clock-names = "tmu_apbif";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
g2d@12800000 {
|
||||
compatible = "samsung,s5pv210-g2d";
|
||||
reg = <0x12800000 0x1000>;
|
||||
interrupts = <0 89 0>;
|
||||
clocks = <&clock 177>, <&clock 277>;
|
||||
clock-names = "sclk_fimg2d", "fimg2d";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@
|
|||
#size-cells = <0>;
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <&ldo20_reg &buck8_reg>;
|
||||
status = "okay";
|
||||
|
||||
num-slots = <1>;
|
||||
|
|
@ -78,6 +79,7 @@
|
|||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <&ldo4_reg &ldo21_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -108,4 +110,199 @@
|
|||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@13860000 {
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
max77686: pmic@09 {
|
||||
compatible = "maxim,max77686";
|
||||
reg = <0x09>;
|
||||
|
||||
voltage-regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "VDD_ALIVE_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "VDDQ_M1_2_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "VDDQ_EXT_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "VDDQ_MMC2_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo5_reg: LDO5 {
|
||||
regulator-name = "VDDQ_MMC1_3_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "VDD10_MPLL_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "VDD10_XPLL_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo11_reg: LDO11 {
|
||||
regulator-name = "VDD18_ABB1_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
regulator-name = "VDD33_USB_3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo13_reg: LDO13 {
|
||||
regulator-name = "VDDQ_C2C_W_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "VDD18_ABB0_2_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "VDD10_HSIC_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo16_reg: LDO16 {
|
||||
regulator-name = "VDD18_HSIC_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo20_reg: LDO20 {
|
||||
regulator-name = "LDO20_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo21_reg: LDO21 {
|
||||
regulator-name = "LDO21_3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo25_reg: LDO25 {
|
||||
regulator-name = "VDDQ_LCD_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-microvolt-offset = <50000>;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "VDDQ_CKEM1_2_1.2V";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "BUCK6_1.35V";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck7_reg: BUCK7 {
|
||||
regulator-name = "BUCK7_2.0V";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck8_reg: BUCK8 {
|
||||
regulator-name = "BUCK8_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -36,6 +36,72 @@
|
|||
enable-active-high;
|
||||
};
|
||||
|
||||
pinctrl@11000000 {
|
||||
keypad_rows: keypad-rows {
|
||||
samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
keypad_cols: keypad-cols {
|
||||
samsung,pins = "gpx1-0", "gpx1-1";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
keypad@100A0000 {
|
||||
samsung,keypad-num-rows = <3>;
|
||||
samsung,keypad-num-columns = <2>;
|
||||
linux,keypad-no-autorepeat;
|
||||
linux,keypad-wakeup;
|
||||
pinctrl-0 = <&keypad_rows &keypad_cols>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
key_home {
|
||||
keypad,row = <0>;
|
||||
keypad,column = <0>;
|
||||
linux,code = <102>;
|
||||
};
|
||||
|
||||
key_down {
|
||||
keypad,row = <0>;
|
||||
keypad,column = <1>;
|
||||
linux,code = <108>;
|
||||
};
|
||||
|
||||
key_up {
|
||||
keypad,row = <1>;
|
||||
keypad,column = <0>;
|
||||
linux,code = <103>;
|
||||
};
|
||||
|
||||
key_menu {
|
||||
keypad,row = <1>;
|
||||
keypad,column = <1>;
|
||||
linux,code = <139>;
|
||||
};
|
||||
|
||||
key_back {
|
||||
keypad,row = <2>;
|
||||
keypad,column = <0>;
|
||||
linux,code = <158>;
|
||||
};
|
||||
|
||||
key_enter {
|
||||
keypad,row = <2>;
|
||||
keypad,column = <1>;
|
||||
linux,code = <28>;
|
||||
};
|
||||
};
|
||||
|
||||
g2d@10800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
|
||||
|
|
|
|||
|
|
@ -31,8 +31,91 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
g2d@10800000 {
|
||||
pinctrl@11000000 {
|
||||
keypad_rows: keypad-rows {
|
||||
samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
keypad_cols: keypad-cols {
|
||||
samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3",
|
||||
"gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
keypad@100A0000 {
|
||||
samsung,keypad-num-rows = <3>;
|
||||
samsung,keypad-num-columns = <8>;
|
||||
linux,keypad-no-autorepeat;
|
||||
linux,keypad-wakeup;
|
||||
pinctrl-0 = <&keypad_rows &keypad_cols>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
key_1 {
|
||||
keypad,row = <1>;
|
||||
keypad,column = <3>;
|
||||
linux,code = <2>;
|
||||
};
|
||||
|
||||
key_2 {
|
||||
keypad,row = <1>;
|
||||
keypad,column = <4>;
|
||||
linux,code = <3>;
|
||||
};
|
||||
|
||||
key_3 {
|
||||
keypad,row = <1>;
|
||||
keypad,column = <5>;
|
||||
linux,code = <4>;
|
||||
};
|
||||
|
||||
key_4 {
|
||||
keypad,row = <1>;
|
||||
keypad,column = <6>;
|
||||
linux,code = <5>;
|
||||
};
|
||||
|
||||
key_5 {
|
||||
keypad,row = <1>;
|
||||
keypad,column = <7>;
|
||||
linux,code = <6>;
|
||||
};
|
||||
|
||||
key_A {
|
||||
keypad,row = <2>;
|
||||
keypad,column = <6>;
|
||||
linux,code = <30>;
|
||||
};
|
||||
|
||||
key_B {
|
||||
keypad,row = <2>;
|
||||
keypad,column = <7>;
|
||||
linux,code = <48>;
|
||||
};
|
||||
|
||||
key_C {
|
||||
keypad,row = <0>;
|
||||
keypad,column = <5>;
|
||||
linux,code = <46>;
|
||||
};
|
||||
|
||||
key_D {
|
||||
keypad,row = <2>;
|
||||
keypad,column = <5>;
|
||||
linux,code = <32>;
|
||||
};
|
||||
|
||||
key_E {
|
||||
keypad,row = <0>;
|
||||
keypad,column = <7>;
|
||||
linux,code = <18>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
|
|
|
|||
|
|
@ -778,62 +778,6 @@
|
|||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
keypad_col0: keypad-col0 {
|
||||
samsung,pins = "gpl2-0";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
keypad_col1: keypad-col1 {
|
||||
samsung,pins = "gpl2-1";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
keypad_col2: keypad-col2 {
|
||||
samsung,pins = "gpl2-2";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
keypad_col3: keypad-col3 {
|
||||
samsung,pins = "gpl2-3";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
keypad_col4: keypad-col4 {
|
||||
samsung,pins = "gpl2-4";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
keypad_col5: keypad-col5 {
|
||||
samsung,pins = "gpl2-5";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
keypad_col6: keypad-col6 {
|
||||
samsung,pins = "gpl2-6";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
keypad_col7: keypad-col7 {
|
||||
samsung,pins = "gpl2-7";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
cam_port_b: cam-port-b {
|
||||
samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
|
||||
"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
|
||||
|
|
|
|||
|
|
@ -28,14 +28,6 @@
|
|||
pinctrl3 = &pinctrl_3;
|
||||
};
|
||||
|
||||
combiner:interrupt-controller@10440000 {
|
||||
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
|
||||
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
|
||||
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
|
||||
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
|
||||
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4412-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
|
|
@ -77,6 +69,8 @@
|
|||
compatible = "samsung,exynos4212-g2d";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 89 0>;
|
||||
clocks = <&clock 177>, <&clock 277>;
|
||||
clock-names = "sclk_fimg2d", "fimg2d";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -449,4 +449,35 @@
|
|||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dp-controller {
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
};
|
||||
|
||||
fimd: fimd@14400000 {
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing@0 {
|
||||
/* 2560x1600 DP panel */
|
||||
clock-frequency = <50000>;
|
||||
hactive = <2560>;
|
||||
vactive = <1600>;
|
||||
hfront-porch = <48>;
|
||||
hback-porch = <80>;
|
||||
hsync-len = <32>;
|
||||
vback-porch = <16>;
|
||||
vfront-porch = <8>;
|
||||
vsync-len = <6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rtc {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -553,6 +553,13 @@
|
|||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
dp_hpd: dp_hpd {
|
||||
samsung,pins = "gpx0-7";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@13400000 {
|
||||
|
|
|
|||
|
|
@ -37,6 +37,30 @@
|
|||
};
|
||||
};
|
||||
|
||||
vdd:fixed-regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd-supply";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dbvdd:fixed-regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dbvdd-supply";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
spkvdd:fixed-regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "spkvdd-supply";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
i2c@12C70000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <20000>;
|
||||
|
|
@ -47,8 +71,17 @@
|
|||
};
|
||||
|
||||
wm8994: wm8994@1a {
|
||||
compatible = "wlf,wm8994";
|
||||
reg = <0x1a>;
|
||||
compatible = "wlf,wm8994";
|
||||
reg = <0x1a>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
AVDD2-supply = <&vdd>;
|
||||
CPVDD-supply = <&vdd>;
|
||||
DBVDD-supply = <&dbvdd>;
|
||||
SPKVDD1-supply = <&spkvdd>;
|
||||
SPKVDD2-supply = <&spkvdd>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -224,6 +257,9 @@
|
|||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dp_hpd>;
|
||||
};
|
||||
|
||||
display-timings {
|
||||
|
|
|
|||
|
|
@ -171,6 +171,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* On Snow we've got SIP WiFi and so can keep drive strengths low to
|
||||
* reduce EMI.
|
||||
|
|
|
|||
|
|
@ -479,6 +479,36 @@
|
|||
pinctrl-0 = <&i2s2_bus>;
|
||||
};
|
||||
|
||||
usb@12000000 {
|
||||
compatible = "samsung,exynos5250-dwusb3";
|
||||
clocks = <&clock 286>;
|
||||
clock-names = "usbdrd30";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
dwc3 {
|
||||
compatible = "synopsys,dwc3";
|
||||
reg = <0x12000000 0x10000>;
|
||||
interrupts = <0 72 0>;
|
||||
usb-phy = <&usb2_phy &usb3_phy>;
|
||||
};
|
||||
};
|
||||
|
||||
usb3_phy: usbphy@12100000 {
|
||||
compatible = "samsung,exynos5250-usb3phy";
|
||||
reg = <0x12100000 0x100>;
|
||||
clocks = <&clock 1>, <&clock 286>;
|
||||
clock-names = "ext_xtal", "usbdrd30";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usbphy-sys {
|
||||
reg = <0x10040704 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
compatible = "samsung,exynos4210-ehci";
|
||||
reg = <0x12110000 0x100>;
|
||||
|
|
@ -497,7 +527,7 @@
|
|||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
usbphy@12130000 {
|
||||
usb2_phy: usbphy@12130000 {
|
||||
compatible = "samsung,exynos5250-usb2phy";
|
||||
reg = <0x12130000 0x100>;
|
||||
clocks = <&clock 1>, <&clock 285>;
|
||||
|
|
@ -621,6 +651,8 @@
|
|||
reg = <0x145b0000 0x1000>;
|
||||
interrupts = <10 3>;
|
||||
interrupt-parent = <&combiner>;
|
||||
clocks = <&clock 342>;
|
||||
clock-names = "dp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
compatible = "samsung,sd5v1", "samsung,exynos5440";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
|
||||
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
|
|
|
|||
|
|
@ -17,11 +17,46 @@
|
|||
compatible = "samsung,ssdk5440", "samsung,exynos5440";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
|
||||
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
|
||||
};
|
||||
|
||||
spi {
|
||||
status = "disabled";
|
||||
spi_0: spi@D0000 {
|
||||
|
||||
flash: w25q128@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "winbond,w25q128";
|
||||
spi-max-frequency = <15625000>;
|
||||
reg = <0>;
|
||||
controller-data {
|
||||
samsung,spi-feedback-delay = <0>;
|
||||
};
|
||||
|
||||
partition@00000 {
|
||||
label = "BootLoader";
|
||||
reg = <0x60000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@e0000 {
|
||||
label = "Recovery-Kernel";
|
||||
reg = <0xe0000 0x300000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@3e0000 {
|
||||
label = "CRAM-FS";
|
||||
reg = <0x3e0000 0x700000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@ae0000 {
|
||||
label = "User-Data";
|
||||
reg = <0xae0000 0x520000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
|
|
|
|||
|
|
@ -16,6 +16,10 @@
|
|||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
spi0 = &spi_0;
|
||||
};
|
||||
|
||||
clock: clock-controller@0x160000 {
|
||||
compatible = "samsung,exynos5440-clock";
|
||||
reg = <0x160000 0x1000>;
|
||||
|
|
@ -38,18 +42,22 @@
|
|||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <2>;
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <3>;
|
||||
};
|
||||
|
|
@ -79,8 +87,13 @@
|
|||
interrupts = <0 57 0>;
|
||||
operating-points = <
|
||||
/* KHz uV */
|
||||
1500000 1100000
|
||||
1400000 1075000
|
||||
1300000 1050000
|
||||
1200000 1025000
|
||||
1100000 1000000
|
||||
1000000 975000
|
||||
900000 950000
|
||||
800000 925000
|
||||
>;
|
||||
};
|
||||
|
|
@ -101,14 +114,14 @@
|
|||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
spi {
|
||||
compatible = "samsung,exynos4210-spi";
|
||||
reg = <0xD0000 0x1000>;
|
||||
spi_0: spi@D0000 {
|
||||
compatible = "samsung,exynos5440-spi";
|
||||
reg = <0xD0000 0x100>;
|
||||
interrupts = <0 4 0>;
|
||||
tx-dma-channel = <&pdma0 5>; /* preliminary */
|
||||
rx-dma-channel = <&pdma0 4>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
samsung,spi-src-clk = <0>;
|
||||
num-cs = <1>;
|
||||
clocks = <&clock 21>, <&clock 16>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
|
@ -184,28 +197,6 @@
|
|||
compatible = "arm,amba-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
pdma0: pdma@00121000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121000 0x1000>;
|
||||
interrupts = <0 46 0>;
|
||||
clocks = <&clock 8>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
};
|
||||
|
||||
pdma1: pdma@00120000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <0 47 0>;
|
||||
clocks = <&clock 8>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc {
|
||||
|
|
@ -214,7 +205,30 @@
|
|||
interrupts = <0 17 0>, <0 16 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata@210000 {
|
||||
compatible = "snps,exynos5440-ahci";
|
||||
reg = <0x210000 0x10000>;
|
||||
interrupts = <0 30 0>;
|
||||
clocks = <&clock 23>;
|
||||
clock-names = "sata";
|
||||
};
|
||||
|
||||
ohci@220000 {
|
||||
compatible = "samsung,exynos5440-ohci";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <0 29 0>;
|
||||
clocks = <&clock 24>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
ehci@221000 {
|
||||
compatible = "samsung,exynos5440-ehci";
|
||||
reg = <0x221000 0x1000>;
|
||||
interrupts = <0 29 0>;
|
||||
clocks = <&clock 24>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
pcie@290000 {
|
||||
|
|
|
|||
|
|
@ -9,7 +9,8 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "dbx5x0.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "dbx5x0.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
|
|
@ -27,7 +28,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
soc-u9500 {
|
||||
soc {
|
||||
uart@80120000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -45,14 +46,14 @@
|
|||
compatible = "tc3589x";
|
||||
reg = <0x42>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <25 0x1>;
|
||||
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
tc3589x_gpio: tc3589x_gpio {
|
||||
compatible = "tc3589x-gpio";
|
||||
interrupts = <0 0x1>;
|
||||
interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -63,17 +64,43 @@
|
|||
};
|
||||
|
||||
i2c@80128000 {
|
||||
lp5521@0x33 {
|
||||
compatible = "lp5521";
|
||||
lp5521@33 {
|
||||
compatible = "national,lp5521";
|
||||
reg = <0x33>;
|
||||
label = "lp5521_pri";
|
||||
clock-mode = /bits/ 8 <2>;
|
||||
chan0 {
|
||||
led-cur = /bits/ 8 <0x2f>;
|
||||
max-cur = /bits/ 8 <0x5f>;
|
||||
};
|
||||
chan1 {
|
||||
led-cur = /bits/ 8 <0x2f>;
|
||||
max-cur = /bits/ 8 <0x5f>;
|
||||
};
|
||||
chan2 {
|
||||
led-cur = /bits/ 8 <0x2f>;
|
||||
max-cur = /bits/ 8 <0x5f>;
|
||||
};
|
||||
};
|
||||
|
||||
lp5521@0x34 {
|
||||
compatible = "lp5521";
|
||||
lp5521@34 {
|
||||
compatible = "national,lp5521";
|
||||
reg = <0x34>;
|
||||
label = "lp5521_sec";
|
||||
clock-mode = /bits/ 8 <2>;
|
||||
chan0 {
|
||||
led-cur = /bits/ 8 <0x2f>;
|
||||
max-cur = /bits/ 8 <0x5f>;
|
||||
};
|
||||
chan1 {
|
||||
led-cur = /bits/ 8 <0x2f>;
|
||||
max-cur = /bits/ 8 <0x5f>;
|
||||
};
|
||||
chan2 {
|
||||
led-cur = /bits/ 8 <0x2f>;
|
||||
max-cur = /bits/ 8 <0x5f>;
|
||||
};
|
||||
};
|
||||
|
||||
bh1780@0x29 {
|
||||
bh1780@29 {
|
||||
compatible = "rohm,bh1780gli";
|
||||
reg = <0x33>;
|
||||
};
|
||||
|
|
@ -82,7 +109,7 @@
|
|||
// External Micro SD slot
|
||||
sdi0_per1@80126000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
max-frequency = <50000000>;
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <4>;
|
||||
mmc-cap-sd-highspeed;
|
||||
mmc-cap-mmc-highspeed;
|
||||
|
|
@ -97,7 +124,7 @@
|
|||
// WLAN SDIO channel
|
||||
sdi1_per2@80118000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
max-frequency = <50000000>;
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <4>;
|
||||
|
||||
status = "okay";
|
||||
|
|
@ -106,7 +133,7 @@
|
|||
// PoP:ed eMMC
|
||||
sdi2_per3@80005000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
max-frequency = <50000000>;
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <8>;
|
||||
mmc-cap-mmc-highspeed;
|
||||
|
||||
|
|
@ -116,7 +143,7 @@
|
|||
// On-board eMMC
|
||||
sdi4_per2@80114000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
max-frequency = <50000000>;
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <8>;
|
||||
mmc-cap-mmc-highspeed;
|
||||
vmmc-supply = <&ab8500_ldo_aux2_reg>;
|
||||
|
|
@ -236,7 +263,7 @@
|
|||
regulator-name = "V-MMC-SD";
|
||||
};
|
||||
|
||||
ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
|
||||
ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
|
||||
regulator-name = "V-INTCORE";
|
||||
};
|
||||
|
||||
|
|
@ -256,7 +283,7 @@
|
|||
regulator-name = "V-AMIC1";
|
||||
};
|
||||
|
||||
ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
|
||||
ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
|
||||
regulator-name = "V-AMIC2";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -10,9 +10,9 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "dbx5x0.dtsi"
|
||||
/include/ "href.dtsi"
|
||||
/include/ "stuib.dtsi"
|
||||
#include "dbx5x0.dtsi"
|
||||
#include "href.dtsi"
|
||||
#include "stuib.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ST-Ericsson HREF (pre-v60) platform with Device Tree";
|
||||
|
|
@ -24,7 +24,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
soc-u9500 {
|
||||
soc {
|
||||
prcmu@80157000 {
|
||||
ab8500@5 {
|
||||
ab8500-gpio {
|
||||
|
|
@ -41,7 +41,7 @@
|
|||
};
|
||||
|
||||
i2c@80110000 {
|
||||
bu21013_tp@0x5c {
|
||||
bu21013_tp@5c {
|
||||
reset-gpio = <&tc3589x_gpio 13 0x4>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,9 +10,9 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "dbx5x0.dtsi"
|
||||
/include/ "href.dtsi"
|
||||
/include/ "stuib.dtsi"
|
||||
#include "dbx5x0.dtsi"
|
||||
#include "href.dtsi"
|
||||
#include "stuib.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ST-Ericsson HREF (v60+) platform with Device Tree";
|
||||
|
|
@ -24,7 +24,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
soc-u9500 {
|
||||
soc {
|
||||
i2c@80110000 {
|
||||
bu21013_tp@0x5c {
|
||||
reset-gpio = <&gpio4 15 0x4>;
|
||||
|
|
@ -34,7 +34,7 @@
|
|||
// External Micro SD slot
|
||||
sdi0_per1@80126000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
max-frequency = <50000000>;
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <4>;
|
||||
mmc-cap-sd-highspeed;
|
||||
mmc-cap-mmc-highspeed;
|
||||
|
|
@ -48,7 +48,7 @@
|
|||
// WLAN SDIO channel
|
||||
sdi1_per2@80118000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
max-frequency = <50000000>;
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <4>;
|
||||
|
||||
status = "okay";
|
||||
|
|
@ -57,7 +57,7 @@
|
|||
// PoP:ed eMMC
|
||||
sdi2_per3@80005000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
max-frequency = <50000000>;
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <8>;
|
||||
mmc-cap-mmc-highspeed;
|
||||
|
||||
|
|
@ -67,7 +67,7 @@
|
|||
// On-board eMMC
|
||||
sdi4_per2@80114000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
max-frequency = <50000000>;
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <8>;
|
||||
mmc-cap-mmc-highspeed;
|
||||
vmmc-supply = <&ab8500_ldo_aux2_reg>;
|
||||
|
|
@ -172,7 +172,7 @@
|
|||
regulator-name = "V-MMC-SD";
|
||||
};
|
||||
|
||||
ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
|
||||
ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
|
||||
regulator-name = "V-INTCORE";
|
||||
};
|
||||
|
||||
|
|
@ -192,7 +192,7 @@
|
|||
regulator-name = "V-AMIC1";
|
||||
};
|
||||
|
||||
ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
|
||||
ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
|
||||
regulator-name = "V-AMIC2";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -23,8 +23,12 @@
|
|||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ejs";
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
37
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
Normal file
37
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx27-phytec-phycore-som.dts"
|
||||
|
||||
/ {
|
||||
model = "Phytec pcm970";
|
||||
compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
|
||||
};
|
||||
|
||||
&cspi1 {
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;
|
||||
};
|
||||
|
||||
&sdhci2 {
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio3 29 0>;
|
||||
wp-gpios = <&gpio3 28 0>;
|
||||
vmmc-supply = <&vmmc1_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
fsl,uart-has-rtscts;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
179
arch/arm/boot/dts/imx27-phytec-phycore-som.dts
Normal file
179
arch/arm/boot/dts/imx27-phytec-phycore-som.dts
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* Copyright 2012 Sascha Hauer, Pengutronix
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx27.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Phytec pcm038";
|
||||
compatible = "phytec,imx27-pcm038", "fsl,imx27";
|
||||
|
||||
memory {
|
||||
reg = <0x0 0x0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
aipi@10000000 { /* aipi1 */
|
||||
serial@1000a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@1001d000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
at24@52 {
|
||||
compatible = "at,24c32";
|
||||
pagesize = <32>;
|
||||
reg = <0x52>;
|
||||
};
|
||||
pcf8563@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
lm75@4a {
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aipi@10020000 { /* aipi2 */
|
||||
ethernet@1002b000 {
|
||||
phy-reset-gpios = <&gpio3 30 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nor_flash@c0000000 {
|
||||
compatible = "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0xc0000000 0x02000000>;
|
||||
linux,mtd-name = "physmap-flash.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cspi1 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio4 28 0>;
|
||||
status = "okay";
|
||||
|
||||
pmic: mc13783@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mc13783";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <23 0x4>;
|
||||
fsl,mc13xxx-uses-adc;
|
||||
fsl,mc13xxx-uses-rtc;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1a {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
sw1b_reg: sw1b {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
sw2a_reg: sw2a {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
sw2b_reg: sw2b {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
sw3_reg: sw3 {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vaudio_reg: vaudio {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
violo_reg: violo {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
viohi_reg: viohi {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vgen_reg: vgen {
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcam_reg: vcam {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
vrf1_reg: vrf1 {
|
||||
regulator-min-microvolt = <2775000>;
|
||||
regulator-max-microvolt = <2775000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vrf2_reg: vrf2 {
|
||||
regulator-min-microvolt = <2775000>;
|
||||
regulator-max-microvolt = <2775000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vmmc1_reg: vmmc1 {
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
gpo1_reg: gpo1 { };
|
||||
|
||||
pwgt1spi_reg: pwgt1spi {
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,79 +0,0 @@
|
|||
/*
|
||||
* Copyright 2012 Sascha Hauer, Pengutronix
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx27.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Phytec pcm038";
|
||||
compatible = "phytec,imx27-pcm038", "fsl,imx27";
|
||||
|
||||
memory {
|
||||
reg = <0x0 0x0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
aipi@10000000 { /* aipi1 */
|
||||
serial@1000a000 {
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@1000b000 {
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@1000c000 {
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@1001d000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
at24@52 {
|
||||
compatible = "at,24c32";
|
||||
pagesize = <32>;
|
||||
reg = <0x52>;
|
||||
};
|
||||
pcf8563@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
lm75@4a {
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aipi@10020000 { /* aipi2 */
|
||||
ethernet@1002b000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nor_flash@c0000000 {
|
||||
compatible = "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0xc0000000 0x02000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -25,6 +25,9 @@
|
|||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
gpio5 = &gpio6;
|
||||
spi0 = &cspi1;
|
||||
spi1 = &cspi2;
|
||||
spi2 = &cspi3;
|
||||
};
|
||||
|
||||
avic: avic-interrupt-controller@e0000000 {
|
||||
|
|
@ -58,6 +61,16 @@
|
|||
reg = <0x10000000 0x20000>;
|
||||
ranges;
|
||||
|
||||
dma: dma@10001000 {
|
||||
compatible = "fsl,imx27-dma";
|
||||
reg = <0x10001000 0x1000>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clks 50>, <&clks 70>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <16>;
|
||||
};
|
||||
|
||||
wdog: wdog@10002000 {
|
||||
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x10002000 0x1000>;
|
||||
|
|
@ -89,6 +102,14 @@
|
|||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm0: pwm@10006000 {
|
||||
compatible = "fsl,imx27-pwm";
|
||||
reg = <0x10006000 0x1000>;
|
||||
interrupts = <23>;
|
||||
clocks = <&clks 34>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
|
|
@ -157,6 +178,28 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci1: sdhci@10013000 {
|
||||
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
|
||||
reg = <0x10013000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&clks 30>, <&clks 60>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&dma 7>;
|
||||
dma-names = "rx-tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci2: sdhci@10014000 {
|
||||
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
|
||||
reg = <0x10014000 0x1000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&clks 29>, <&clks 60>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&dma 6>;
|
||||
dma-names = "rx-tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@10015000 {
|
||||
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
||||
reg = <0x10015000 0x100>;
|
||||
|
|
@ -272,6 +315,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci3: sdhci@1001e000 {
|
||||
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
|
||||
reg = <0x1001e000 0x1000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&clks 28>, <&clks 60>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&dma 36>;
|
||||
dma-names = "rx-tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt6: timer@1001f000 {
|
||||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x1001f000 0x1000>;
|
||||
|
|
@ -288,6 +342,21 @@
|
|||
reg = <0x10020000 0x20000>;
|
||||
ranges;
|
||||
|
||||
coda: coda@10023000 {
|
||||
compatible = "fsl,imx27-vpu";
|
||||
reg = <0x10023000 0x0200>;
|
||||
interrupts = <53>;
|
||||
clocks = <&clks 57>, <&clks 66>;
|
||||
clock-names = "per", "ahb";
|
||||
iram = <&iram>;
|
||||
};
|
||||
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
fec: ethernet@1002b000 {
|
||||
compatible = "fsl,imx27-fec";
|
||||
reg = <0x1002b000 0x4000>;
|
||||
|
|
@ -296,19 +365,16 @@
|
|||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
iram: iram@ffff4c00 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0xffff4c00 0xb400>;
|
||||
};
|
||||
|
||||
nfc: nand@d8000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "fsl,imx27-nand";
|
||||
reg = <0xd8000000 0x1000>;
|
||||
interrupts = <29>;
|
||||
|
|
|
|||
|
|
@ -103,6 +103,7 @@
|
|||
|
||||
apbx@80040000 {
|
||||
lradc@80050000 {
|
||||
fsl,lradc-touchscreen-wires = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -45,6 +45,17 @@
|
|||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
usb0_otg_cfa10036: otg-10036@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x0142 /* MX28_PAD_GPMI_READY0__USB0_ID */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
ssp0: ssp@80010000 {
|
||||
|
|
@ -58,12 +69,6 @@
|
|||
};
|
||||
|
||||
apbx@80040000 {
|
||||
pwm: pwm@80064000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
duart: serial@80074000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&duart_pins_b>;
|
||||
|
|
@ -73,15 +78,30 @@
|
|||
i2c0: i2c@80058000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_b>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
ssd1307: oled@3c {
|
||||
compatible = "solomon,ssd1307fb-i2c";
|
||||
ssd1306: oled@3c {
|
||||
compatible = "solomon,ssd1306fb-i2c";
|
||||
reg = <0x3c>;
|
||||
pwms = <&pwm 4 3000>;
|
||||
reset-gpios = <&gpio2 7 0>;
|
||||
solomon,height = <32>;
|
||||
solomon,width = <128>;
|
||||
solomon,page-offset = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
usbphy0: usbphy@8007c000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ahb@80080000 {
|
||||
usb0: usb@80080000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb0_otg_cfa10036>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@
|
|||
0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
|
||||
0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
|
||||
0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
|
||||
0x3173 /* MX28_PAD_LCD_RESET__GPIO_3_23 */
|
||||
0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
|
|
@ -166,8 +166,8 @@
|
|||
|
||||
apbx@80040000 {
|
||||
pwm: pwm@80064000 {
|
||||
pinctrl-names = "default", "default";
|
||||
pinctrl-1 = <&pwm3_pins_b>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_pins_b>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -265,7 +265,7 @@
|
|||
gpio-sck = <&gpio2 16 0>;
|
||||
gpio-mosi = <&gpio2 17 0>;
|
||||
gpio-miso = <&gpio2 18 0>;
|
||||
cs-gpios = <&gpio3 23 0>;
|
||||
cs-gpios = <&gpio3 5 0>;
|
||||
num-chipselects = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
179
arch/arm/boot/dts/imx28-cfa10055.dts
Normal file
179
arch/arm/boot/dts/imx28-cfa10055.dts
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* Copyright 2013 Crystalfontz America, Inc.
|
||||
* Free Electrons
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/*
|
||||
* The CFA-10055 is an expansion board for the CFA-10036 module and
|
||||
* CFA-10037, thus we need to include the CFA-10037 DTS.
|
||||
*/
|
||||
/include/ "imx28-cfa10037.dts"
|
||||
|
||||
/ {
|
||||
model = "Crystalfontz CFA-10055 Board";
|
||||
compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
|
||||
|
||||
apb@80000000 {
|
||||
apbh@80000000 {
|
||||
pinctrl@80018000 {
|
||||
pinctrl-names = "default", "default";
|
||||
pinctrl-1 = <&hog_pins_cfa10055
|
||||
&hog_pins_cfa10055_pullup>;
|
||||
|
||||
hog_pins_cfa10055: hog-10055@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
hog_pins_cfa10055_pullup: hog-10055-pullup@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
|
||||
spi2_pins_cfa10055: spi2-cfa10055@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */
|
||||
0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */
|
||||
0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */
|
||||
>;
|
||||
fsl,drive-strength = <1>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
|
||||
lcdif_18bit_pins_cfa10055: lcdif-18bit@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
|
||||
0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
|
||||
0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
|
||||
0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
|
||||
0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
|
||||
0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
|
||||
0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
|
||||
0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
|
||||
0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
|
||||
0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
|
||||
0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
|
||||
0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
|
||||
0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
|
||||
0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
|
||||
0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
|
||||
0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
|
||||
0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
|
||||
0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
lcdif_pins_cfa10055: lcdif-evk@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
|
||||
0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
|
||||
0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
|
||||
0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
lcdif@80030000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcdif_18bit_pins_cfa10055
|
||||
&lcdif_pins_cfa10055>;
|
||||
display = <&display>;
|
||||
status = "okay";
|
||||
|
||||
display: display {
|
||||
bits-per-pixel = <32>;
|
||||
bus-width = <18>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <9216000>;
|
||||
hactive = <320>;
|
||||
vactive = <480>;
|
||||
hback-porch = <2>;
|
||||
hfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vfront-porch = <2>;
|
||||
hsync-len = <15>;
|
||||
vsync-len = <15>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
apbx@80040000 {
|
||||
lradc@80050000 {
|
||||
fsl,lradc-touchscreen-wires = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm: pwm@80064000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_pins_b>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi2 {
|
||||
compatible = "spi-gpio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_pins_cfa10055>;
|
||||
status = "okay";
|
||||
gpio-sck = <&gpio2 16 0>;
|
||||
gpio-mosi = <&gpio2 17 0>;
|
||||
gpio-miso = <&gpio2 18 0>;
|
||||
cs-gpios = <&gpio3 5 0>;
|
||||
num-chipselects = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hx8357: hx8357@0 {
|
||||
compatible = "himax,hx8357b", "himax,hx8357";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <100000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
gpios-reset = <&gpio3 30 0>;
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm 3 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
};
|
||||
};
|
||||
191
arch/arm/boot/dts/imx28-cfa10057.dts
Normal file
191
arch/arm/boot/dts/imx28-cfa10057.dts
Normal file
|
|
@ -0,0 +1,191 @@
|
|||
/*
|
||||
* Copyright 2013 Crystalfontz America, Inc.
|
||||
* Copyright 2012 Free Electrons
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/*
|
||||
* The CFA-10057 is an expansion board for the CFA-10036 module, thus we
|
||||
* need to include the CFA-10036 DTS.
|
||||
*/
|
||||
/include/ "imx28-cfa10036.dts"
|
||||
|
||||
/ {
|
||||
model = "Crystalfontz CFA-10057 Board";
|
||||
compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28";
|
||||
|
||||
apb@80000000 {
|
||||
apbh@80000000 {
|
||||
pinctrl@80018000 {
|
||||
pinctrl-names = "default", "default";
|
||||
pinctrl-1 = <&hog_pins_cfa10057
|
||||
&hog_pins_cfa10057_pullup>;
|
||||
|
||||
hog_pins_cfa10057: hog-10057@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
|
||||
0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
hog_pins_cfa10057_pullup: hog-10057-pullup@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */
|
||||
0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */
|
||||
0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */
|
||||
0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */
|
||||
0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
|
||||
lcdif_18bit_pins_cfa10057: lcdif-18bit@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
|
||||
0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
|
||||
0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
|
||||
0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
|
||||
0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
|
||||
0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
|
||||
0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
|
||||
0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
|
||||
0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
|
||||
0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
|
||||
0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
|
||||
0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
|
||||
0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
|
||||
0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
|
||||
0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
|
||||
0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
|
||||
0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
|
||||
0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
lcdif_pins_cfa10057: lcdif-evk@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
|
||||
0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
|
||||
0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
|
||||
0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
lcdif@80030000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcdif_18bit_pins_cfa10057
|
||||
&lcdif_pins_cfa10057>;
|
||||
display = <&display>;
|
||||
status = "okay";
|
||||
|
||||
display: display {
|
||||
bits-per-pixel = <32>;
|
||||
bus-width = <18>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <30000000>;
|
||||
hactive = <480>;
|
||||
vactive = <800>;
|
||||
hfront-porch = <12>;
|
||||
hback-porch = <2>;
|
||||
vfront-porch = <5>;
|
||||
vback-porch = <3>;
|
||||
hsync-len = <2>;
|
||||
vsync-len = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
apbx@80040000 {
|
||||
lradc@80050000 {
|
||||
fsl,lradc-touchscreen-wires = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm: pwm@80064000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_pins_b>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@8005a000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@8007e000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ahb@80080000 {
|
||||
usb1: usb@80090000 {
|
||||
vbus-supply = <®_usb1_vbus>;
|
||||
pinctrl-0 = <&usbphy1_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_usb1_vbus: usb1_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio0 7 1>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb@80080000 {
|
||||
mac0: ethernet@800f0000 {
|
||||
phy-mode = "rmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mac0_pins_a>;
|
||||
phy-reset-gpios = <&gpio2 21 0>;
|
||||
phy-reset-duration = <100>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm 3 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <7>;
|
||||
};
|
||||
};
|
||||
|
|
@ -220,7 +220,19 @@
|
|||
|
||||
auart0: serial@8006a000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&auart0_2pins_a>;
|
||||
pinctrl-0 = <&auart0_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
auart1: serial@8006c000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&auart1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
auart2: serial@8006e000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&auart2_2pins_b>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -32,8 +32,12 @@
|
|||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ejs";
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -330,6 +334,17 @@
|
|||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
auart2_2pins_b: auart2-2pins@1 {
|
||||
reg = <1>;
|
||||
fsl,pinmux-ids = <
|
||||
0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
|
||||
0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
auart3_pins_a: auart3@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
|
|
@ -354,6 +369,28 @@
|
|||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
auart3_2pins_b: auart3-2pins@1 {
|
||||
reg = <1>;
|
||||
fsl,pinmux-ids = <
|
||||
0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
|
||||
0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
auart4_2pins_a: auart4@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */
|
||||
0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
mac0_pins_a: mac0@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
|
|
@ -669,7 +706,7 @@
|
|||
};
|
||||
|
||||
digctl@8001c000 {
|
||||
compatible = "fsl,imx28-digctl";
|
||||
compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
|
||||
reg = <0x8001c000 0x2000>;
|
||||
interrupts = <89>;
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -45,6 +45,13 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&nfc {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3_2>;
|
||||
|
|
|
|||
|
|
@ -175,10 +175,20 @@
|
|||
};
|
||||
};
|
||||
|
||||
usbphy0: usbphy@0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks 124>;
|
||||
clock-names = "main_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbotg: usb@73f80000 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80000 0x0200>;
|
||||
interrupts = <18>;
|
||||
clocks = <&clks 108>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
fsl,usbphy = <&usbphy0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -186,6 +196,8 @@
|
|||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80200 0x0200>;
|
||||
interrupts = <14>;
|
||||
clocks = <&clks 108>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -193,6 +205,8 @@
|
|||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80400 0x0200>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clks 108>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -200,9 +214,18 @@
|
|||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80600 0x0200>;
|
||||
interrupts = <17>;
|
||||
clocks = <&clks 108>;
|
||||
fsl,usbmisc = <&usbmisc 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc: usbmisc@73f80800 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx51-usbmisc";
|
||||
reg = <0x73f80800 0x200>;
|
||||
clocks = <&clks 108>;
|
||||
};
|
||||
|
||||
gpio1: gpio@73f84000 {
|
||||
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x73f84000 0x4000>;
|
||||
|
|
|
|||
259
arch/arm/boot/dts/imx53-m53evk.dts
Normal file
259
arch/arm/boot/dts/imx53-m53evk.dts
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "DENX M53EVK";
|
||||
compatible = "denx,imx53-m53evk", "fsl,imx53";
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x20000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
display@di1 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
crtcs = <&ipu 1>;
|
||||
interface-pix-fmt = "bgr666";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
|
||||
|
||||
display-timings {
|
||||
800x480p60 {
|
||||
native-mode;
|
||||
clock-frequency = <31500000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <40>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
vback-porch = <33>;
|
||||
vfront-porch = <9>;
|
||||
vsync-len = <3>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 3000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_pin_gpio>;
|
||||
|
||||
user1 {
|
||||
label = "user1";
|
||||
gpios = <&gpio2 8 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
user2 {
|
||||
label = "user2";
|
||||
gpios = <&gpio2 9 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_3p2v: 3p2v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P2V";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx53-m53evk-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx53-m53evk-sgtl5000";
|
||||
ssi-controller = <&ssi2>;
|
||||
audio-codec = <&sgtl5000>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"LINE_IN", "Line In Jack",
|
||||
"Headphone Jack", "HP_OUT",
|
||||
"Ext Spk", "LINE_OUT";
|
||||
mux-int-port = <2>;
|
||||
mux-ext-port = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux_2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can2_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_1>;
|
||||
cd-gpios = <&gpio1 1 0>;
|
||||
wp-gpios = <&gpio1 9 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_1>;
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1_2>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
VDDA-supply = <®_3p2v>;
|
||||
VDDIO-supply = <®_3p2v>;
|
||||
clocks = <&clks 150>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_2>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
stmpe610@41 {
|
||||
compatible = "st,stmpe610";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x41>;
|
||||
id = <0>;
|
||||
blocks = <0x5>;
|
||||
interrupts = <6 0x0>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
irq-trigger = <0x1>;
|
||||
|
||||
stmpe_touchscreen {
|
||||
compatible = "stmpe,ts";
|
||||
reg = <0>;
|
||||
ts,sample-time = <4>;
|
||||
ts,mod-12b = <1>;
|
||||
ts,ref-sel = <0>;
|
||||
ts,adc-freq = <1>;
|
||||
ts,ave-ctrl = <3>;
|
||||
ts,touch-det-delay = <3>;
|
||||
ts,settling = <4>;
|
||||
ts,fraction-z = <7>;
|
||||
ts,i-drive = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c128";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
|
||||
rtc: rtc@68 {
|
||||
compatible = "stm,m41t62";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
|
||||
|
||||
>;
|
||||
};
|
||||
|
||||
led_pin_gpio: led_gpio@0 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000
|
||||
MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand_1>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -16,27 +16,81 @@
|
|||
/ {
|
||||
model = "TQ MBa53 starter kit";
|
||||
compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
|
||||
|
||||
reg_backlight: fixed@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd-supply";
|
||||
gpio = <&gpio2 5 0>;
|
||||
startup-delay-us = <5000>;
|
||||
enable-active-low;
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 50000 0 0>;
|
||||
brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
|
||||
default-brightness-level = <10>;
|
||||
enable-gpios = <&gpio7 7 0>;
|
||||
power-supply = <®_backlight>;
|
||||
};
|
||||
|
||||
disp1: display@disp1 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp1_1>;
|
||||
crtcs = <&ipu 1>;
|
||||
interface-pix-fmt = "rgb24";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
reg_3p2v: 3p2v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P2V";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "tq,imx53-mba53-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx53-mba53-sgtl5000";
|
||||
ssi-controller = <&ssi2>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <2>;
|
||||
mux-ext-port = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lvds1_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
lvds1 {
|
||||
pinctrl_lvds1_1: lvds1-grp1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
|
||||
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
|
||||
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
|
||||
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
|
||||
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
|
||||
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
|
||||
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
|
||||
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
|
||||
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
|
||||
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lvds1_2: lvds1-grp2 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
|
||||
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
|
||||
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
|
||||
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
|
||||
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
|
||||
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
|
||||
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
|
||||
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
|
||||
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
|
||||
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -44,33 +98,44 @@
|
|||
disp1 {
|
||||
pinctrl_disp1_1: disp1-grp1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */
|
||||
MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */
|
||||
MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000
|
||||
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */
|
||||
MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */
|
||||
MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
tve {
|
||||
pinctrl_vga_sync_1: vgasync-grp1 {
|
||||
fsl,pins = <
|
||||
/* VGA_VSYNC, HSYNC with max drive strength */
|
||||
MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6
|
||||
MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -80,16 +145,27 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&audmux {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux_1>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
codec: sgtl5000@a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 150>;
|
||||
VDDA-supply = <®_3p2v>;
|
||||
VDDIO-supply = <®_3p2v>;
|
||||
};
|
||||
|
||||
expander: pca9554@20 {
|
||||
compatible = "pca9554";
|
||||
reg = <0x20>;
|
||||
interrupts = <109>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
sensor2: lm75@49 {
|
||||
|
|
@ -99,6 +175,7 @@
|
|||
};
|
||||
|
||||
&fec {
|
||||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -114,10 +191,24 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -133,3 +224,13 @@
|
|||
&i2c3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tve {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_vga_sync_1>;
|
||||
ddc = <&i2c3>;
|
||||
fsl,tve-mode = "vga";
|
||||
fsl,hsync-pin = <4>;
|
||||
fsl,vsync-pin = <6>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,6 +21,33 @@
|
|||
reg = <0x70000000 0x40000000>;
|
||||
};
|
||||
|
||||
display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
crtcs = <&ipu 0>;
|
||||
interface-pix-fmt = "rgb565";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp0_1>;
|
||||
status = "disabled";
|
||||
display-timings {
|
||||
claawvga {
|
||||
native-mode;
|
||||
clock-frequency = <27000000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <40>;
|
||||
hfront-porch = <60>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <10>;
|
||||
hsync-len = <20>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
|
@ -147,6 +174,7 @@
|
|||
reg = <0x0a>;
|
||||
VDDA-supply = <®_3p2v>;
|
||||
VDDIO-supply = <®_3p2v>;
|
||||
clocks = <&clks 150>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -268,3 +296,11 @@
|
|||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -35,7 +35,9 @@
|
|||
|
||||
&esdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2_1>;
|
||||
pinctrl-0 = <&pinctrl_esdhc2_1>,
|
||||
<&pinctrl_tqma53_esdhc2_2>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
wp-gpios = <&gpio1 2 0>;
|
||||
cd-gpios = <&gpio1 4 0>;
|
||||
status = "disabled";
|
||||
|
|
@ -69,14 +71,22 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
esdhc2_2 {
|
||||
pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
|
||||
MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s {
|
||||
pinctrl_i2s_1: i2s-grp1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_19__GPIO4_5 0x10000 /* I2S_MCLK */
|
||||
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x10000 /* I2S_SCLK */
|
||||
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x10000 /* I2S_DOUT */
|
||||
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */
|
||||
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x10000 /* I2S_DIN */
|
||||
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 /* I2S_SCLK */
|
||||
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 /* I2S_DOUT */
|
||||
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */
|
||||
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 /* I2S_DIN */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -84,16 +94,17 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x10000 /* VSYNC */
|
||||
MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */
|
||||
MX53_PAD_PATA_DA_1__GPIO7_7 0x10000 /* LCD_BLT_EN */
|
||||
MX53_PAD_PATA_DA_2__GPIO7_8 0x10000 /* LCD_RESET */
|
||||
MX53_PAD_PATA_DATA5__GPIO2_5 0x10000 /* LCD_POWER */
|
||||
MX53_PAD_PATA_DATA6__GPIO2_6 0x10000 /* PMIC_INT */
|
||||
MX53_PAD_PATA_DATA14__GPIO2_14 0x10000 /* CSI_RST */
|
||||
MX53_PAD_PATA_DATA15__GPIO2_15 0x10000 /* CSI_PWDN */
|
||||
MX53_PAD_GPIO_0__GPIO1_0 0x10000 /* SYSTEM_DOWN */
|
||||
MX53_PAD_GPIO_3__GPIO1_3 0x10000
|
||||
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
|
||||
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */
|
||||
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */
|
||||
MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */
|
||||
MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */
|
||||
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */
|
||||
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */
|
||||
MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */
|
||||
MX53_PAD_GPIO_3__GPIO1_3 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */
|
||||
MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -149,7 +160,7 @@
|
|||
reg = <0x8>;
|
||||
fsl,mc13xxx-uses-rtc;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <6 8>; /* PDATA_DATA6, low active */
|
||||
interrupts = <6 4>; /* PATA_DATA6, active high */
|
||||
};
|
||||
|
||||
sensor1: lm75@48 {
|
||||
|
|
|
|||
122
arch/arm/boot/dts/imx53-tx53.dtsi
Normal file
122
arch/arm/boot/dts/imx53-tx53.dtsi
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro TX53";
|
||||
compatible = "karo,tx53", "fsl,imx53";
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x40000000>; /* Up to 1GiB */
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_3p3v: 3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can2_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&esdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_1>;
|
||||
phy-mode = "rmii";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&owire {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_owire_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_2>,
|
||||
<&pinctrl_uart1_3>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2_2>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3_1>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -27,6 +27,9 @@
|
|||
gpio4 = &gpio5;
|
||||
gpio5 = &gpio6;
|
||||
gpio6 = &gpio7;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
};
|
||||
|
||||
tzic: tz-interrupt-controller@0fffc000 {
|
||||
|
|
@ -163,10 +166,27 @@
|
|||
};
|
||||
};
|
||||
|
||||
usbphy0: usbphy@0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks 124>;
|
||||
clock-names = "main_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks 125>;
|
||||
clock-names = "main_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbotg: usb@53f80000 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80000 0x0200>;
|
||||
interrupts = <18>;
|
||||
clocks = <&clks 108>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
fsl,usbphy = <&usbphy0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -174,6 +194,9 @@
|
|||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80200 0x0200>;
|
||||
interrupts = <14>;
|
||||
clocks = <&clks 108>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -181,6 +204,8 @@
|
|||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80400 0x0200>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clks 108>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -188,9 +213,18 @@
|
|||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80600 0x0200>;
|
||||
interrupts = <17>;
|
||||
clocks = <&clks 108>;
|
||||
fsl,usbmisc = <&usbmisc 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc: usbmisc@53f80800 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx53-usbmisc";
|
||||
reg = <0x53f80800 0x200>;
|
||||
clocks = <&clks 108>;
|
||||
};
|
||||
|
||||
gpio1: gpio@53f84000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53f84000 0x4000>;
|
||||
|
|
@ -267,6 +301,24 @@
|
|||
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux_2: audmuxgrp-2 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
|
||||
MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
|
||||
MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
|
||||
MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux_3: audmuxgrp-3 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
|
||||
MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
|
||||
MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
|
||||
MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
fec {
|
||||
|
|
@ -284,6 +336,29 @@
|
|||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec_2: fecgrp-2 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
|
||||
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
|
||||
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
|
||||
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
|
||||
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
|
||||
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
|
||||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
|
||||
MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
|
||||
MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
|
||||
MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
|
||||
MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
|
||||
MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
|
||||
MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
|
||||
MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
|
||||
MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
csi {
|
||||
|
|
@ -312,6 +387,22 @@
|
|||
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_csi_2: csigrp-2 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
|
||||
MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
|
||||
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
|
||||
MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
|
||||
MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
|
||||
MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
|
||||
MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
|
||||
MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
|
||||
MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
|
||||
MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
|
||||
MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
cspi {
|
||||
|
|
@ -322,6 +413,14 @@
|
|||
MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_cspi_2: cspigrp-2 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
|
||||
MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
|
||||
MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
|
|
@ -332,6 +431,27 @@
|
|||
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1_2: ecspi1grp-2 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
|
||||
MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
|
||||
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
|
||||
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
|
||||
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
|
||||
MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi2 {
|
||||
pinctrl_ecspi2_1: ecspi2grp-1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
|
||||
MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
|
||||
MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc1 {
|
||||
|
|
@ -406,6 +526,13 @@
|
|||
MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can1_3: can1grp-3 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
|
||||
MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
can2 {
|
||||
|
|
@ -424,6 +551,13 @@
|
|||
MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_2: i2c1grp-2 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
|
||||
MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
|
|
@ -433,6 +567,13 @@
|
|||
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_2: i2c2grp-2 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
|
||||
MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3 {
|
||||
|
|
@ -444,6 +585,119 @@
|
|||
};
|
||||
};
|
||||
|
||||
ipu_disp0 {
|
||||
pinctrl_ipu_disp0_1: ipudisp0grp-1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
|
||||
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
|
||||
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
|
||||
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
|
||||
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
|
||||
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
|
||||
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
|
||||
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
|
||||
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
|
||||
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
|
||||
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
|
||||
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
|
||||
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
|
||||
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
|
||||
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
|
||||
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
|
||||
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
|
||||
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
|
||||
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
|
||||
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
|
||||
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
|
||||
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
|
||||
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
|
||||
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
|
||||
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
|
||||
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
|
||||
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
|
||||
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu_disp1 {
|
||||
pinctrl_ipu_disp1_1: ipudisp1grp-1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
|
||||
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
|
||||
MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
|
||||
MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
|
||||
MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
|
||||
MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
|
||||
MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
|
||||
MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu_disp2 {
|
||||
pinctrl_ipu_disp2_1: ipudisp2grp-1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
|
||||
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
|
||||
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
|
||||
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
|
||||
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
|
||||
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
|
||||
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
|
||||
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
|
||||
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
|
||||
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
nand {
|
||||
pinctrl_nand_1: nandgrp-1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
|
||||
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
|
||||
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
|
||||
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
|
||||
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
|
||||
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
|
||||
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
|
||||
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
|
||||
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
|
||||
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
|
||||
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
|
||||
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
|
||||
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
|
||||
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
|
||||
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
owire {
|
||||
pinctrl_owire_1: owiregrp-1 {
|
||||
fsl,pins = <
|
||||
|
|
@ -452,6 +706,22 @@
|
|||
};
|
||||
};
|
||||
|
||||
pwm1 {
|
||||
pinctrl_pwm1_1: pwm1grp-1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2 {
|
||||
pinctrl_pwm2_1: pwm2grp-1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
|
|
@ -466,6 +736,13 @@
|
|||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1_3: uart1grp-3 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
|
||||
MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
|
|
@ -475,6 +752,15 @@
|
|||
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2_2: uart2grp-2 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
|
||||
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
|
||||
MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
|
||||
MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
|
|
@ -513,7 +799,6 @@
|
|||
>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@53fa8000 {
|
||||
|
|
@ -781,6 +1066,16 @@
|
|||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tve: tve@63ff0000 {
|
||||
compatible = "fsl,imx53-tve";
|
||||
reg = <0x63ff0000 0x1000>;
|
||||
interrupts = <92>;
|
||||
clocks = <&clks 69>, <&clks 116>;
|
||||
clock-names = "tve", "di_sel";
|
||||
crtcs = <&ipu 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,4 +28,12 @@
|
|||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
|
||||
MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
|
||||
MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
|
||||
MX6DL_PAD_GPIO_0__CCM_CLKO1 0x130b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue