A pile of Qualcomm clk driver fixes with two main themes: the alpha PLL
driver and shared RCGs, and one fix for the Starfive JH7110 SoC.
- The Alpha PLL clk_ops had multiple problems around setting rates.
There are a handful of patches here that fix masks and skip enabling
the clk from set_rate() when the PLL is disabled. The PLLs are
crucial to operation of the system as almost all frequencies in the
system are derived from them.
- Parking shared RCGs at a slow always on clk at registration time
breaks stuff. USB host mode can't handle such a slow frequency and
the serial console gets all garbled when the UART clk is handed over
to the kernel. There's a few patches that don't use the shared
clk_ops for the UART clks and another one to skip parking the USB clk
at registration time.
- The Starfive PLL driver used for the CPU was busted causing cpufreq
to fail because the clk didn't change to a safe parent during
set_rate(). The fix is to register a notifier and switch to a safe
parent so the PLL can change rate in a glitch free manner.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmbcmQ4RHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSViNg/9EgJ1GKbhIK3D0oclmp0VX0XAP2+nVn1V
5KVP/hBzzxUMlFIXi4PLBuHSGwb9LvKNXGCU0vRRCODxuMHhu404LqVZ42ZAOP5e
mTVYnH600AN2OJOSZO7HApTTwW9/N7hHCe7Rxw4ueZIPx7sCyjo/mBrppWho3rqg
TEfqtJ0IpXp41U10wr5fM5cF3YCmAJmR0Qoj7tow4D+wDiz25+l6maIuJQAPJyRY
NR7Z8Q25Q5sy7sxgDNtNXKJxo16DnX1b9Ye+Uyb2RBtF0JmgsdH68ga78jnhrW1J
37HbLD5u8Td6zUJ9qUu5TvrXQeOACFElOGvFmke0YchXtJad50VM2/QgFPondWjY
P8y15HQLKngXcfqzlVRGwy89kkhh1+PfomcIkSq5hUDr2W++K1pnSBEPxZ2lyfZi
NSmcgt3Cm19gj5/HkYFgfhZwjpnHPQ/P5tNYjSeIbYTGVVx4NkjlnRyR5vYuURkM
9HMY3qr12mleeSiTDqtsSUxTCqXUgnHyFovQZLO2Nru2pMrR2kKzWiR0ZGODYBwn
w3FLeSPOg89L1NldCMBvWY+KMG8ouRkfYT88tJX9ckWflP6MgpZsLXxV81BIW5fm
JHvZ/ZMdKPnGdKF1CnjYqNtGK+1AeOZf5VBK/tNRJv//vtk9S/VzfG1XoUw+vLrF
YBN3oP4Pbeg=
=ypMR
-----END PGP SIGNATURE-----
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A pile of Qualcomm clk driver fixes with two main themes: the alpha
PLL driver and shared RCGs, and one fix for the Starfive JH7110 SoC.
- The Alpha PLL clk_ops had multiple problems around setting rates.
There are a handful of patches here that fix masks and skip
enabling the clk from set_rate() when the PLL is disabled. The PLLs
are crucial to operation of the system as almost all frequencies in
the system are derived from them.
- Parking shared RCGs at a slow always on clk at registration time
breaks stuff.
USB host mode can't handle such a slow frequency and the serial
console gets all garbled when the UART clk is handed over to the
kernel. There's a few patches that don't use the shared clk_ops for
the UART clks and another one to skip parking the USB clk at
registration time.
- The Starfive PLL driver used for the CPU was busted causing cpufreq
to fail because the clk didn't change to a safe parent during
set_rate().
The fix is to register a notifier and switch to a safe parent so
the PLL can change rate in a glitch free manner"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: gcc-sc8280xp: don't use parking clk_ops for QUPs
clk: starfive: jh7110-sys: Add notifier for PLL0 clock
clk: qcom: gcc-sm8650: Don't use shared clk_ops for QUPs
clk: qcom: gcc-sm8550: Don't park the USB RCG at registration time
clk: qcom: gcc-sm8550: Don't use parking clk_ops for QUPs
clk: qcom: gcc-x1e80100: Don't use parking clk_ops for QUPs
clk: qcom: ipq9574: Update the alpha PLL type for GPLLs
clk: qcom: gcc-x1e80100: Fix USB 0 and 1 PHY GDSC pwrsts flags
clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL
clk: qcom: clk-alpha-pll: Fix zonda set_rate failure when PLL is disabled
clk: qcom: clk-alpha-pll: Fix the trion pll postdiv set rate API
clk: qcom: clk-alpha-pll: Fix the pll post div mask
This commit is contained in:
Linus Torvalds
commit
d1f2d51b71
10 changed files with 196 additions and 115 deletions
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@ -40,7 +40,8 @@
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#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
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# define PLL_POST_DIV_SHIFT 8
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# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
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# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
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# define PLL_ALPHA_MSB BIT(15)
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# define PLL_ALPHA_EN BIT(24)
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# define PLL_ALPHA_MODE BIT(25)
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# define PLL_VCO_SHIFT 20
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@ -1552,8 +1553,8 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
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}
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return regmap_update_bits(regmap, PLL_USER_CTL(pll),
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PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
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val << PLL_POST_DIV_SHIFT);
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PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
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val << pll->post_div_shift);
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}
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const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
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@ -2117,6 +2118,18 @@ static void clk_zonda_pll_disable(struct clk_hw *hw)
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regmap_write(regmap, PLL_OPMODE(pll), 0x0);
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}
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static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l)
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{
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u64 remainder, quotient;
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quotient = rate;
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remainder = do_div(quotient, prate);
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*l = quotient;
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if ((remainder * 2) / prate)
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*l = *l + 1;
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}
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static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate)
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{
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@ -2133,9 +2146,15 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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if (ret < 0)
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return ret;
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if (a & PLL_ALPHA_MSB)
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zonda_pll_adjust_l_val(rate, prate, &l);
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regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
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regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
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if (!clk_hw_is_enabled(hw))
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return 0;
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/* Wait before polling for the frequency latch */
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udelay(5);
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@ -198,6 +198,7 @@ extern const struct clk_ops clk_byte2_ops;
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extern const struct clk_ops clk_pixel_ops;
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extern const struct clk_ops clk_gfx3d_ops;
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extern const struct clk_ops clk_rcg2_shared_ops;
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extern const struct clk_ops clk_rcg2_shared_no_init_park_ops;
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extern const struct clk_ops clk_dp_ops;
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struct clk_rcg_dfs_data {
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@ -1348,6 +1348,36 @@ const struct clk_ops clk_rcg2_shared_ops = {
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
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static int clk_rcg2_shared_no_init_park(struct clk_hw *hw)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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/*
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* Read the config register so that the parent is properly mapped at
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* registration time.
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*/
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg);
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return 0;
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}
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/*
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* Like clk_rcg2_shared_ops but skip the init so that the clk frequency is left
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* unchanged at registration time.
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*/
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const struct clk_ops clk_rcg2_shared_no_init_park_ops = {
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.init = clk_rcg2_shared_no_init_park,
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.enable = clk_rcg2_shared_enable,
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.disable = clk_rcg2_shared_disable,
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.get_parent = clk_rcg2_shared_get_parent,
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.set_parent = clk_rcg2_shared_set_parent,
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.recalc_rate = clk_rcg2_shared_recalc_rate,
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.determine_rate = clk_rcg2_determine_rate,
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.set_rate = clk_rcg2_shared_set_rate,
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.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_shared_no_init_park_ops);
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/* Common APIs to be used for DFS based RCGR */
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static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
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struct freq_tbl *f)
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@ -68,7 +68,7 @@ static const struct clk_parent_data gcc_sleep_clk_data[] = {
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static struct clk_alpha_pll gpll0_main = {
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.offset = 0x20000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
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.clkr = {
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.enable_reg = 0x0b000,
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.enable_mask = BIT(0),
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@ -96,7 +96,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
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static struct clk_alpha_pll_postdiv gpll0 = {
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.offset = 0x20000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "gpll0",
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@ -110,7 +110,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
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static struct clk_alpha_pll gpll4_main = {
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.offset = 0x22000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
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.clkr = {
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.enable_reg = 0x0b000,
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.enable_mask = BIT(2),
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@ -125,7 +125,7 @@ static struct clk_alpha_pll gpll4_main = {
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static struct clk_alpha_pll_postdiv gpll4 = {
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.offset = 0x22000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "gpll4",
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@ -139,7 +139,7 @@ static struct clk_alpha_pll_postdiv gpll4 = {
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static struct clk_alpha_pll gpll2_main = {
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.offset = 0x21000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
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.clkr = {
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.enable_reg = 0x0b000,
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.enable_mask = BIT(1),
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@ -154,7 +154,7 @@ static struct clk_alpha_pll gpll2_main = {
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static struct clk_alpha_pll_postdiv gpll2 = {
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.offset = 0x21000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "gpll2",
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@ -1500,7 +1500,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
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@ -1517,7 +1517,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
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@ -1534,7 +1534,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
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@ -1551,7 +1551,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
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@ -1568,7 +1568,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
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@ -1585,7 +1585,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
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@ -1617,7 +1617,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
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@ -1634,7 +1634,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
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@ -1651,7 +1651,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
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@ -1668,7 +1668,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
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@ -1685,7 +1685,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
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@ -1702,7 +1702,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
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|
@ -1719,7 +1719,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
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.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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.ops = &clk_rcg2_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
||||
|
|
@ -1736,7 +1736,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
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.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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||||
.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
||||
|
|
@ -1753,7 +1753,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
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||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
|
||||
|
|
@ -1770,7 +1770,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
|
||||
|
|
@ -1787,7 +1787,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
||||
|
|
@ -1804,7 +1804,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
||||
|
|
@ -1821,7 +1821,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
|
||||
|
|
@ -1838,7 +1838,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
||||
|
|
@ -1855,7 +1855,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
||||
|
|
@ -1872,7 +1872,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
||||
|
|
@ -1889,7 +1889,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
|
||||
|
|
@ -1906,7 +1906,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
|
||||
|
|
|
|||
|
|
@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
|
||||
|
|
@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
|
||||
|
|
@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
|
||||
|
|
@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
|
||||
|
|
@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
||||
|
|
@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
||||
|
|
@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
|
||||
|
|
@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
|
||||
|
|
@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
||||
|
|
@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
||||
|
|
@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
|
||||
|
|
@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
||||
|
|
@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
||||
|
|
@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
||||
|
|
@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_8,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
|
||||
|
|
@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
|
||||
|
|
@ -1159,7 +1159,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_shared_no_init_park_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -713,7 +713,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -728,7 +728,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -743,7 +743,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -758,7 +758,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -773,7 +773,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -788,7 +788,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -803,7 +803,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -818,7 +818,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -833,7 +833,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -848,7 +848,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -863,7 +863,7 @@ static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = {
|
||||
|
|
@ -899,7 +899,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
|
||||
|
|
@ -916,7 +916,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
|
||||
|
|
@ -948,7 +948,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
|
||||
|
|
@ -980,7 +980,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
||||
|
|
@ -997,7 +997,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
||||
|
|
@ -1014,7 +1014,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
|
||||
|
|
@ -1031,7 +1031,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
|
||||
|
|
@ -1059,7 +1059,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_ibi_ctrl_0_clk_src = {
|
|||
.parent_data = gcc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1068,7 +1068,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
||||
|
|
@ -1085,7 +1085,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
||||
|
|
@ -1102,7 +1102,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
|
||||
|
|
@ -1119,7 +1119,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
||||
|
|
@ -1136,7 +1136,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
||||
|
|
@ -1153,7 +1153,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
||||
|
|
@ -1186,7 +1186,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_10,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
|
||||
|
|
@ -1203,7 +1203,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
|
||||
|
|
@ -1226,7 +1226,7 @@ static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = {
|
||||
|
|
|
|||
|
|
@ -670,7 +670,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
|
||||
|
|
@ -687,7 +687,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
|
||||
|
|
@ -719,7 +719,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
|
||||
|
|
@ -736,7 +736,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
|
||||
|
|
@ -768,7 +768,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
|
||||
|
|
@ -785,7 +785,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
|
||||
|
|
@ -802,7 +802,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
|
||||
|
|
@ -819,7 +819,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
|
||||
|
|
@ -836,7 +836,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
|
||||
|
|
@ -853,7 +853,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
|
||||
|
|
@ -870,7 +870,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
|
||||
|
|
@ -887,7 +887,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
|
||||
|
|
@ -904,7 +904,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
||||
|
|
@ -921,7 +921,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
||||
|
|
@ -938,7 +938,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
|
||||
|
|
@ -955,7 +955,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
|
||||
|
|
@ -972,7 +972,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
||||
|
|
@ -989,7 +989,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
||||
|
|
@ -1006,7 +1006,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
|
||||
|
|
@ -1023,7 +1023,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
||||
|
|
@ -1040,7 +1040,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
||||
|
|
@ -1057,7 +1057,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
||||
|
|
@ -1074,7 +1074,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_8,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
|
||||
|
|
@ -1091,7 +1091,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
|
|||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
|
||||
|
|
@ -6203,7 +6203,7 @@ static struct gdsc gcc_usb_0_phy_gdsc = {
|
|||
.pd = {
|
||||
.name = "gcc_usb_0_phy_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
|
|
@ -6215,7 +6215,7 @@ static struct gdsc gcc_usb_1_phy_gdsc = {
|
|||
.pd = {
|
||||
.name = "gcc_usb_1_phy_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
|
||||
|
||||
/*
|
||||
* This clock notifier is called when the rate of PLL0 clock is to be changed.
|
||||
* The cpu_root clock should save the curent parent clock and switch its parent
|
||||
* clock to osc before PLL0 rate will be changed. Then switch its parent clock
|
||||
* back after the PLL0 rate is completed.
|
||||
*/
|
||||
static int jh7110_pll0_clk_notifier_cb(struct notifier_block *nb,
|
||||
unsigned long action, void *data)
|
||||
{
|
||||
struct jh71x0_clk_priv *priv = container_of(nb, struct jh71x0_clk_priv, pll_clk_nb);
|
||||
struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk;
|
||||
int ret = 0;
|
||||
|
||||
if (action == PRE_RATE_CHANGE) {
|
||||
struct clk *osc = clk_get(priv->dev, "osc");
|
||||
|
||||
priv->original_clk = clk_get_parent(cpu_root);
|
||||
ret = clk_set_parent(cpu_root, osc);
|
||||
clk_put(osc);
|
||||
} else if (action == POST_RATE_CHANGE) {
|
||||
ret = clk_set_parent(cpu_root, priv->original_clk);
|
||||
}
|
||||
|
||||
return notifier_from_errno(ret);
|
||||
}
|
||||
|
||||
static int __init jh7110_syscrg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct jh71x0_clk_priv *priv;
|
||||
|
|
@ -413,7 +439,10 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(priv->pll[0]))
|
||||
return PTR_ERR(priv->pll[0]);
|
||||
} else {
|
||||
clk_put(pllclk);
|
||||
priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb;
|
||||
ret = clk_notifier_register(pllclk, &priv->pll_clk_nb);
|
||||
if (ret)
|
||||
return ret;
|
||||
priv->pll[0] = NULL;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -114,6 +114,8 @@ struct jh71x0_clk_priv {
|
|||
spinlock_t rmw_lock;
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
struct clk *original_clk;
|
||||
struct notifier_block pll_clk_nb;
|
||||
struct clk_hw *pll[3];
|
||||
struct jh71x0_clk reg[];
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue