Blaster4385/linux-IllusionX
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue

Browse source 
Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2023-05-17 (ice, MAINTAINERS)

This series contains updates to ice driver and MAINTAINERS file.

Paul refactors PHY to link mode reporting and updates some PHY types to
report more accurate link modes for ice.

Dave removes mutual exclusion policy between LAG and SR-IOV in ice
driver.

Jesse updates link for Intel Wired LAN in the MAINTAINERS file.

* '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
  MAINTAINERS: update Intel Ethernet links
  ice: Remove LAG+SRIOV mutual exclusion
  ice: update PHY type to ethtool link mode mapping
  ice: refactor PHY type to ethtool link mode
  ice: update ICE_PHY_TYPE_HIGH_MAX_INDEX
====================

Link: https://lore.kernel.org/r/20230517165530.3179965-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2023-05-18 20:04:59 -07:00
commit bf9233f913
10 changed files with 144 additions and 387 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
Documentation/networking/device_drivers/ethernet/intel/ice.rst
View file

@ -84,24 +84,6 @@ Once the VM shuts down, or otherwise releases the VF, the command will
complete.
Important notes for SR-IOV and Link Aggregation
-----------------------------------------------
Link Aggregation is mutually exclusive with SR-IOV.
- If Link Aggregation is active, SR-IOV VFs cannot be created on the PF.
- If SR-IOV is active, you cannot set up Link Aggregation on the interface.
Bridging and MACVLAN are also affected by this. If you wish to use bridging or
MACVLAN with SR-IOV, you must set up bridging or MACVLAN before enabling
SR-IOV. If you are using bridging or MACVLAN in conjunction with SR-IOV, and
you want to remove the interface from the bridge or MACVLAN, you must follow
these steps:
1. Destroy SR-IOV VFs if they exist
2. Remove the interface from the bridge or MACVLAN
3. Recreate SRIOV VFs as needed
Additional Features and Configurations
======================================

5
MAINTAINERS
View file

@ -10337,9 +10337,8 @@ M: Jesse Brandeburg <jesse.brandeburg@intel.com>
M: Tony Nguyen <anthony.l.nguyen@intel.com>
L: intel-wired-lan@lists.osuosl.org (moderated for non-subscribers)
S: Supported
W: http://www.intel.com/support/feedback.htm
W: http://e1000.sourceforge.net/
Q: http://patchwork.ozlabs.org/project/intel-wired-lan/list/
W: https://www.intel.com/content/www/us/en/support.html
Q: https://patchwork.ozlabs.org/project/intel-wired-lan/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue.git
F: Documentation/networking/device_drivers/ethernet/intel/

20
drivers/net/ethernet/intel/ice/ice.h
View file

@ -32,6 +32,7 @@
#include <linux/pkt_sched.h>
#include <linux/if_bridge.h>
#include <linux/ctype.h>
#include <linux/linkmode.h>
#include <linux/bpf.h>
#include <linux/btf.h>
#include <linux/auxiliary_bus.h>
@ -813,25 +814,6 @@ static inline bool ice_is_switchdev_running(struct ice_pf *pf)
return pf->switchdev.is_running;
}
/**
* ice_set_sriov_cap - enable SRIOV in PF flags
* @pf: PF struct
*/
static inline void ice_set_sriov_cap(struct ice_pf *pf)
{
if (pf->hw.func_caps.common_cap.sr_iov_1_1)
set_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);
}
/**
* ice_clear_sriov_cap - disable SRIOV in PF flags
* @pf: PF struct
*/
static inline void ice_clear_sriov_cap(struct ice_pf *pf)
{
clear_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);
}
#define ICE_FD_STAT_CTR_BLOCK_COUNT 256
#define ICE_FD_STAT_PF_IDX(base_idx) \
((base_idx) * ICE_FD_STAT_CTR_BLOCK_COUNT)

2
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
View file

@ -1087,7 +1087,7 @@ struct ice_aqc_get_phy_caps {
#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
#define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
#define ICE_PHY_TYPE_HIGH_MAX_INDEX 4
struct ice_aqc_get_phy_caps_data {
__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */

309
drivers/net/ethernet/intel/ice/ice_ethtool.c
View file

@ -4,6 +4,7 @@
/* ethtool support for ice */
#include "ice.h"
#include "ice_ethtool.h"
#include "ice_flow.h"
#include "ice_fltr.h"
#include "ice_lib.h"
@ -1658,15 +1659,26 @@ ice_mask_min_supported_speeds(struct ice_hw *hw,
*phy_types_low &= ~ICE_PHY_TYPE_LOW_MASK_MIN_1G;
}
#define ice_ethtool_advertise_link_mode(aq_link_speed, ethtool_link_mode) \
do { \
if (req_speeds & (aq_link_speed) || \
(!req_speeds && \
(advert_phy_type_lo & phy_type_mask_lo || \
advert_phy_type_hi & phy_type_mask_hi))) \
ethtool_link_ksettings_add_link_mode(ks, advertising,\
ethtool_link_mode); \
} while (0)
/**
* ice_linkmode_set_bit - set link mode bit
* @phy_to_ethtool: PHY type to ethtool link mode struct to set
* @ks: ethtool link ksettings struct to fill out
* @req_speeds: speed requested by user
* @advert_phy_type: advertised PHY type
* @phy_type: PHY type
*/
static void
ice_linkmode_set_bit(const struct ice_phy_type_to_ethtool *phy_to_ethtool,
struct ethtool_link_ksettings *ks, u32 req_speeds,
u64 advert_phy_type, u32 phy_type)
{
linkmode_set_bit(phy_to_ethtool->link_mode, ks->link_modes.supported);
if (req_speeds & phy_to_ethtool->aq_link_speed ||
(!req_speeds && advert_phy_type & BIT(phy_type)))
linkmode_set_bit(phy_to_ethtool->link_mode,
ks->link_modes.advertising);
}
/**
* ice_phy_type_to_ethtool - convert the phy_types to ethtool link modes
@ -1682,11 +1694,10 @@ ice_phy_type_to_ethtool(struct net_device *netdev,
struct ice_pf *pf = vsi->back;
u64 advert_phy_type_lo = 0;
u64 advert_phy_type_hi = 0;
u64 phy_type_mask_lo = 0;
u64 phy_type_mask_hi = 0;
u64 phy_types_high = 0;
u64 phy_types_low = 0;
u16 req_speeds;
u32 req_speeds;
u32 i;
req_speeds = vsi->port_info->phy.link_info.req_speeds;
@ -1743,272 +1754,22 @@ ice_phy_type_to_ethtool(struct net_device *netdev,
advert_phy_type_hi = vsi->port_info->phy.phy_type_high;
}
ethtool_link_ksettings_zero_link_mode(ks, supported);
ethtool_link_ksettings_zero_link_mode(ks, advertising);
linkmode_zero(ks->link_modes.supported);
linkmode_zero(ks->link_modes.advertising);
phy_type_mask_lo = ICE_PHY_TYPE_LOW_100BASE_TX |
ICE_PHY_TYPE_LOW_100M_SGMII;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100baseT_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100MB,
100baseT_Full);
for (i = 0; i < BITS_PER_TYPE(u64); i++) {
if (phy_types_low & BIT_ULL(i))
ice_linkmode_set_bit(&phy_type_low_lkup[i], ks,
req_speeds, advert_phy_type_lo,
i);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_1000BASE_T |
ICE_PHY_TYPE_LOW_1G_SGMII;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
1000baseT_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_1000MB,
1000baseT_Full);
for (i = 0; i < BITS_PER_TYPE(u64); i++) {
if (phy_types_high & BIT_ULL(i))
ice_linkmode_set_bit(&phy_type_high_lkup[i], ks,
req_speeds, advert_phy_type_hi,
i);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_1000BASE_KX;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
1000baseKX_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_1000MB,
1000baseKX_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_1000BASE_SX |
ICE_PHY_TYPE_LOW_1000BASE_LX;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
1000baseX_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_1000MB,
1000baseX_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_2500BASE_T;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
2500baseT_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_2500MB,
2500baseT_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_2500BASE_X |
ICE_PHY_TYPE_LOW_2500BASE_KX;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
2500baseX_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_2500MB,
2500baseX_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_5GBASE_T |
ICE_PHY_TYPE_LOW_5GBASE_KR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
5000baseT_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_5GB,
5000baseT_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_T |
ICE_PHY_TYPE_LOW_10G_SFI_DA |
ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC |
ICE_PHY_TYPE_LOW_10G_SFI_C2C;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
10000baseT_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,
10000baseT_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_KR_CR1;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
10000baseKR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,
10000baseKR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_SR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
10000baseSR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,
10000baseSR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_LR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
10000baseLR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,
10000baseLR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_25GBASE_T |
ICE_PHY_TYPE_LOW_25GBASE_CR |
ICE_PHY_TYPE_LOW_25GBASE_CR_S |
ICE_PHY_TYPE_LOW_25GBASE_CR1 |
ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC |
ICE_PHY_TYPE_LOW_25G_AUI_C2C;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
25000baseCR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_25GB,
25000baseCR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_25GBASE_SR |
ICE_PHY_TYPE_LOW_25GBASE_LR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
25000baseSR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_25GB,
25000baseSR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_25GBASE_KR |
ICE_PHY_TYPE_LOW_25GBASE_KR_S |
ICE_PHY_TYPE_LOW_25GBASE_KR1;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
25000baseKR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_25GB,
25000baseKR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_KR4;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
40000baseKR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,
40000baseKR4_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_CR4 |
ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC |
ICE_PHY_TYPE_LOW_40G_XLAUI;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
40000baseCR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,
40000baseCR4_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_SR4;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
40000baseSR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,
40000baseSR4_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_LR4;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
40000baseLR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,
40000baseLR4_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_50GBASE_CR2 |
ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC |
ICE_PHY_TYPE_LOW_50G_LAUI2 |
ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC |
ICE_PHY_TYPE_LOW_50G_AUI2 |
ICE_PHY_TYPE_LOW_50GBASE_CP |
ICE_PHY_TYPE_LOW_50GBASE_SR |
ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC |
ICE_PHY_TYPE_LOW_50G_AUI1;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
50000baseCR2_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_50GB,
50000baseCR2_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_50GBASE_KR2 |
ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
50000baseKR2_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_50GB,
50000baseKR2_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_50GBASE_SR2 |
ICE_PHY_TYPE_LOW_50GBASE_LR2 |
ICE_PHY_TYPE_LOW_50GBASE_FR |
ICE_PHY_TYPE_LOW_50GBASE_LR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
50000baseSR2_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_50GB,
50000baseSR2_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_100GBASE_CR4 |
ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC |
ICE_PHY_TYPE_LOW_100G_CAUI4 |
ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC |
ICE_PHY_TYPE_LOW_100G_AUI4 |
ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4;
phy_type_mask_hi = ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC |
ICE_PHY_TYPE_HIGH_100G_CAUI2 |
ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC |
ICE_PHY_TYPE_HIGH_100G_AUI2;
if (phy_types_low & phy_type_mask_lo ||
phy_types_high & phy_type_mask_hi) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseCR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseCR4_Full);
}
if (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_CP2) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseCR2_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseCR2_Full);
}
if (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_SR4) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseSR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseSR4_Full);
}
if (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_SR2) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseSR2_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseSR2_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_100GBASE_LR4 |
ICE_PHY_TYPE_LOW_100GBASE_DR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseLR4_ER4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseLR4_ER4_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_100GBASE_KR4 |
ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseKR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseKR4_Full);
}
if (phy_types_high & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseKR2_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseKR2_Full);
}
}
#define TEST_SET_BITS_TIMEOUT 50

105
drivers/net/ethernet/intel/ice/ice_ethtool.h Normal file
View file

@ -0,0 +1,105 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (C) 2023 Intel Corporation */
#ifndef _ICE_ETHTOOL_H_
#define _ICE_ETHTOOL_H_
struct ice_phy_type_to_ethtool {
u64 aq_link_speed;
u8 link_mode;
};
/* Macro to make PHY type to Ethtool link mode table entry.
* The index is the PHY type.
*/
#define ICE_PHY_TYPE(LINK_SPEED, ETHTOOL_LINK_MODE) {\
.aq_link_speed = ICE_AQ_LINK_SPEED_##LINK_SPEED, \
.link_mode = ETHTOOL_LINK_MODE_##ETHTOOL_LINK_MODE##_BIT, \
}
/* Lookup table mapping PHY type low to link speed and Ethtool link modes.
* Array index corresponds to HW PHY type bit, see
* ice_adminq_cmd.h:ICE_PHY_TYPE_LOW_*.
*/
static const struct ice_phy_type_to_ethtool
phy_type_low_lkup[] = {
[0] = ICE_PHY_TYPE(100MB, 100baseT_Full),
[1] = ICE_PHY_TYPE(100MB, 100baseT_Full),
[2] = ICE_PHY_TYPE(1000MB, 1000baseT_Full),
[3] = ICE_PHY_TYPE(1000MB, 1000baseX_Full),
[4] = ICE_PHY_TYPE(1000MB, 1000baseX_Full),
[5] = ICE_PHY_TYPE(1000MB, 1000baseKX_Full),
[6] = ICE_PHY_TYPE(1000MB, 1000baseT_Full),
[7] = ICE_PHY_TYPE(2500MB, 2500baseT_Full),
[8] = ICE_PHY_TYPE(2500MB, 2500baseX_Full),
[9] = ICE_PHY_TYPE(2500MB, 2500baseX_Full),
[10] = ICE_PHY_TYPE(5GB, 5000baseT_Full),
[11] = ICE_PHY_TYPE(5GB, 5000baseT_Full),
[12] = ICE_PHY_TYPE(10GB, 10000baseT_Full),
[13] = ICE_PHY_TYPE(10GB, 10000baseCR_Full),
[14] = ICE_PHY_TYPE(10GB, 10000baseSR_Full),
[15] = ICE_PHY_TYPE(10GB, 10000baseLR_Full),
[16] = ICE_PHY_TYPE(10GB, 10000baseKR_Full),
[17] = ICE_PHY_TYPE(10GB, 10000baseCR_Full),
[18] = ICE_PHY_TYPE(10GB, 10000baseKR_Full),
[19] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
[20] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
[21] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
[22] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
[23] = ICE_PHY_TYPE(25GB, 25000baseSR_Full),
[24] = ICE_PHY_TYPE(25GB, 25000baseSR_Full),
[25] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
[26] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
[27] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
[28] = ICE_PHY_TYPE(25GB, 25000baseSR_Full),
[29] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
[30] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
[31] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
[32] = ICE_PHY_TYPE(40GB, 40000baseLR4_Full),
[33] = ICE_PHY_TYPE(40GB, 40000baseKR4_Full),
[34] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
[35] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
[36] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[37] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
[38] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
[39] = ICE_PHY_TYPE(50GB, 50000baseKR2_Full),
[40] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
[41] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[42] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
[43] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[44] = ICE_PHY_TYPE(50GB, 50000baseCR_Full),
[45] = ICE_PHY_TYPE(50GB, 50000baseSR_Full),
[46] = ICE_PHY_TYPE(50GB, 50000baseLR_ER_FR_Full),
[47] = ICE_PHY_TYPE(50GB, 50000baseLR_ER_FR_Full),
[48] = ICE_PHY_TYPE(50GB, 50000baseKR_Full),
[49] = ICE_PHY_TYPE(50GB, 50000baseSR_Full),
[50] = ICE_PHY_TYPE(50GB, 50000baseCR_Full),
[51] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[52] = ICE_PHY_TYPE(100GB, 100000baseSR4_Full),
[53] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full),
[54] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full),
[55] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[56] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[57] = ICE_PHY_TYPE(100GB, 100000baseSR4_Full),
[58] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[59] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[60] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full),
[61] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
[62] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
[63] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full),
};
/* Lookup table mapping PHY type high to link speed and Ethtool link modes.
* Array index corresponds to HW PHY type bit, see
* ice_adminq_cmd.h:ICE_PHY_TYPE_HIGH_*
*/
static const struct ice_phy_type_to_ethtool
phy_type_high_lkup[] = {
[0] = ICE_PHY_TYPE(100GB, 100000baseKR2_Full),
[1] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
[2] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
[3] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
[4] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
};
#endif /* !_ICE_ETHTOOL_H_ */

12
drivers/net/ethernet/intel/ice/ice_lag.c
View file

@ -6,15 +6,6 @@
#include "ice.h"
#include "ice_lag.h"
/**
* ice_lag_nop_handler - no-op Rx handler to disable LAG
* @pskb: pointer to skb pointer
*/
rx_handler_result_t ice_lag_nop_handler(struct sk_buff __always_unused **pskb)
{
return RX_HANDLER_PASS;
}
/**
* ice_lag_set_primary - set PF LAG state as Primary
* @lag: LAG info struct
@ -158,7 +149,6 @@ ice_lag_link(struct ice_lag *lag, struct netdev_notifier_changeupper_info *info)
lag->upper_netdev = upper;
}
ice_clear_sriov_cap(pf);
ice_clear_rdma_cap(pf);
lag->bonded = true;
@ -205,7 +195,6 @@ ice_lag_unlink(struct ice_lag *lag,
}
lag->peer_netdev = NULL;
ice_set_sriov_cap(pf);
ice_set_rdma_cap(pf);
lag->bonded = false;
lag->role = ICE_LAG_NONE;
@ -229,7 +218,6 @@ static void ice_lag_unregister(struct ice_lag *lag, struct net_device *netdev)
if (lag->upper_netdev) {
dev_put(lag->upper_netdev);
lag->upper_netdev = NULL;
ice_set_sriov_cap(pf);
ice_set_rdma_cap(pf);
}
/* perform some cleanup in case we come back */

54
drivers/net/ethernet/intel/ice/ice_lag.h
View file

@ -25,63 +25,9 @@ struct ice_lag {
struct notifier_block notif_block;
u8 bonded:1; /* currently bonded */
u8 primary:1; /* this is primary */
u8 handler:1; /* did we register a rx_netdev_handler */
/* each thing blocking bonding will increment this value by one.
* If this value is zero, then bonding is allowed.
*/
u16 dis_lag;
u8 role;
};
int ice_init_lag(struct ice_pf *pf);
void ice_deinit_lag(struct ice_pf *pf);
rx_handler_result_t ice_lag_nop_handler(struct sk_buff **pskb);
/**
* ice_disable_lag - increment LAG disable count
* @lag: LAG struct
*/
static inline void ice_disable_lag(struct ice_lag *lag)
{
/* If LAG this PF is not already disabled, disable it */
rtnl_lock();
if (!netdev_is_rx_handler_busy(lag->netdev)) {
if (!netdev_rx_handler_register(lag->netdev,
ice_lag_nop_handler,
NULL))
lag->handler = true;
}
rtnl_unlock();
lag->dis_lag++;
}
/**
* ice_enable_lag - decrement disable count for a PF
* @lag: LAG struct
*
* Decrement the disable counter for a port, and if that count reaches
* zero, then remove the no-op Rx handler from that netdev
*/
static inline void ice_enable_lag(struct ice_lag *lag)
{
if (lag->dis_lag)
lag->dis_lag--;
if (!lag->dis_lag && lag->handler) {
rtnl_lock();
netdev_rx_handler_unregister(lag->netdev);
rtnl_unlock();
lag->handler = false;
}
}
/**
* ice_is_lag_dis - is LAG disabled
* @lag: LAG struct
*
* Return true if bonding is disabled
*/
static inline bool ice_is_lag_dis(struct ice_lag *lag)
{
return !!(lag->dis_lag);
}
#endif /* _ICE_LAG_H_ */

2
drivers/net/ethernet/intel/ice/ice_lib.c
View file

@ -2712,8 +2712,6 @@ ice_vsi_setup(struct ice_pf *pf, struct ice_vsi_cfg_params *params)
return vsi;
err_vsi_cfg:
if (params->type == ICE_VSI_VF)
ice_enable_lag(pf->lag);
ice_vsi_free(vsi);
return NULL;

4
drivers/net/ethernet/intel/ice/ice_sriov.c
View file

@ -979,8 +979,6 @@ int ice_sriov_configure(struct pci_dev *pdev, int num_vfs)
if (!num_vfs) {
if (!pci_vfs_assigned(pdev)) {
ice_free_vfs(pf);
if (pf->lag)
ice_enable_lag(pf->lag);
return 0;
}
@ -992,8 +990,6 @@ int ice_sriov_configure(struct pci_dev *pdev, int num_vfs)
if (err)
return err;
if (pf->lag)
ice_disable_lag(pf->lag);
return num_vfs;
}