linux-can-next-for-5.14-20210527
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Merge tag 'linux-can-next-for-5.14-20210527' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next
Marc Kleine-Budde says:
====================
can-next 2021-05-27
The first 2 patches are by Geert Uytterhoeven and convert the rcan_can
and rcan_canfd device tree bindings to yaml.
The next 2 patches are by Oliver Hartkopp and me and update the CAN
uapi headers.
zuoqilin's patch removes an unnecessary variable from the CAN proc
code.
Patrick Menschel contributes 3 patches for CAN ISOTP to enhance the
error messages.
Jiapeng Chong's patch removes two dead stores from the softing driver.
The next 4 patches are by me and silence several warnings found by
clang compiler.
Jimmy Assarsson's patches for the kvaser_usb driver add support for
the Kvaser hydra devices.
Dario Binacchi provides 2 patches for the c_can driver, first removing
an unused variable, then adding basic ethtool support to query driver
and ring parameter info.
The last 4 patches are by Torin Cooper-Bennun and clean up the m_can
driver.
* tag 'linux-can-next-for-5.14-20210527' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next: (21 commits)
can: m_can: fix whitespace in a few comments
can: m_can: make TXESC, RXESC config more explicit
can: m_can: clean up CCCR reg defs, order by revs
can: m_can: use bits.h macros for all regmasks
can: c_can: add ethtool support
can: c_can: remove unused variable struct c_can_priv::rxmasked
can: kvaser_usb: Add new Kvaser hydra devices
can: kvaser_usb: Rename define USB_HYBRID_{,PRO_}CANLIN_PRODUCT_ID
can: at91_can: silence clang warning
can: mcp251xfd: silence clang warning
can: mcp251x: mcp251x_can_probe(): silence clang warning
can: hi311x: hi3110_can_probe(): silence clang warning
can: softing: Remove redundant variable ptr
can: isotp: Add error message if txqueuelen is too small
can: isotp: add symbolic error message to isotp_module_init()
can: isotp: change error format from decimal to symbolic error names
can: proc: remove unnecessary variables
can: uapi: introduce CANFD_FDF flag for mixed content in struct canfd_frame
can: uapi: update CAN-FD frame description
dt-bindings: can: rcar_canfd: Convert to json-schema
...
====================
Link: https://lore.kernel.org/r/20210527084532.1384031-1-mkl@pengutronix.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
b14b27fffa
19 changed files with 463 additions and 347 deletions
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@ -1,80 +0,0 @@
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Renesas R-Car CAN controller Device Tree Bindings
|
||||
-------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: "renesas,can-r8a7742" if CAN controller is a part of R8A7742 SoC.
|
||||
"renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC.
|
||||
"renesas,can-r8a7744" if CAN controller is a part of R8A7744 SoC.
|
||||
"renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
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"renesas,can-r8a77470" if CAN controller is a part of R8A77470 SoC.
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"renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC.
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"renesas,can-r8a774b1" if CAN controller is a part of R8A774B1 SoC.
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"renesas,can-r8a774c0" if CAN controller is a part of R8A774C0 SoC.
|
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"renesas,can-r8a774e1" if CAN controller is a part of R8A774E1 SoC.
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"renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
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"renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
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"renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC.
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"renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC.
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"renesas,can-r8a7792" if CAN controller is a part of R8A7792 SoC.
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"renesas,can-r8a7793" if CAN controller is a part of R8A7793 SoC.
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"renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC.
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"renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC.
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"renesas,can-r8a7796" if CAN controller is a part of R8A77960 SoC.
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"renesas,can-r8a77961" if CAN controller is a part of R8A77961 SoC.
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"renesas,can-r8a77965" if CAN controller is a part of R8A77965 SoC.
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"renesas,can-r8a77990" if CAN controller is a part of R8A77990 SoC.
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"renesas,can-r8a77995" if CAN controller is a part of R8A77995 SoC.
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"renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device.
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"renesas,rcar-gen2-can" for a generic R-Car Gen2 or RZ/G1
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compatible device.
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"renesas,rcar-gen3-can" for a generic R-Car Gen3 or RZ/G2
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compatible device.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first
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followed by the generic version.
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- reg: physical base address and size of the R-Car CAN register map.
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- interrupts: interrupt specifier for the sole interrupt.
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- clocks: phandles and clock specifiers for 3 CAN clock inputs.
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- clock-names: 3 clock input name strings: "clkp1", "clkp2", and "can_clk".
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- pinctrl-0: pin control group to be used for this controller.
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- pinctrl-names: must be "default".
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Required properties for R8A774A1, R8A774B1, R8A774C0, R8A774E1, R8A7795,
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R8A77960, R8A77961, R8A77965, R8A77990, and R8A77995:
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For the denoted SoCs, "clkp2" can be CANFD clock. This is a div6 clock and can
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be used by both CAN and CAN FD controller at the same time. It needs to be
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scaled to maximum frequency if any of these controllers use it. This is done
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using the below properties:
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- assigned-clocks: phandle of clkp2(CANFD) clock.
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- assigned-clock-rates: maximum frequency of this clock.
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Optional properties:
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- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
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<0x0> (default) : Peripheral clock (clkp1)
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<0x1> : Peripheral clock (clkp2)
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<0x3> : External input clock
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Example
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-------
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SoC common .dtsi file:
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can0: can@e6e80000 {
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compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
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reg = <0 0xe6e80000 0 0x1000>;
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interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
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<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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status = "disabled";
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};
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Board specific .dts file:
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&can0 {
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pinctrl-0 = <&can0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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@ -1,107 +0,0 @@
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Renesas R-Car CAN FD controller Device Tree Bindings
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----------------------------------------------------
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Required properties:
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- compatible: Must contain one or more of the following:
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- "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers.
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- "renesas,r8a774a1-canfd" for R8A774A1 (RZ/G2M) compatible controller.
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- "renesas,r8a774b1-canfd" for R8A774B1 (RZ/G2N) compatible controller.
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- "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller.
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- "renesas,r8a774e1-canfd" for R8A774E1 (RZ/G2H) compatible controller.
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- "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
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- "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
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- "renesas,r8a77965-canfd" for R8A77965 (R-Car M3-N) compatible controller.
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- "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller.
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- "renesas,r8a77980-canfd" for R8A77980 (R-Car V3H) compatible controller.
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- "renesas,r8a77990-canfd" for R8A77990 (R-Car E3) compatible controller.
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- "renesas,r8a77995-canfd" for R8A77995 (R-Car D3) compatible controller.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first, followed by the
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family-specific and/or generic versions.
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- reg: physical base address and size of the R-Car CAN FD register map.
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- interrupts: interrupt specifiers for the Channel & Global interrupts
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- clocks: phandles and clock specifiers for 3 clock inputs.
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- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
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- pinctrl-0: pin control group to be used for this controller.
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- pinctrl-names: must be "default".
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Required child nodes:
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The controller supports two channels and each is represented as a child node.
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The name of the child nodes are "channel0" and "channel1" respectively. Each
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child node supports the "status" property only, which is used to
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enable/disable the respective channel.
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Required properties for R8A774A1, R8A774B1, R8A774C0, R8A774E1, R8A7795,
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R8A7796, R8A77965, R8A77990, and R8A77995:
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In the denoted SoCs, canfd clock is a div6 clock and can be used by both CAN
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and CAN FD controller at the same time. It needs to be scaled to maximum
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frequency if any of these controllers use it. This is done using the below
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properties:
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- assigned-clocks: phandle of canfd clock.
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- assigned-clock-rates: maximum frequency of this clock.
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Optional property:
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The controller can operate in either CAN FD only mode (default) or
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Classical CAN only mode. The mode is global to both the channels. In order to
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enable the later, define the following optional property.
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- renesas,no-can-fd: puts the controller in Classical CAN only mode.
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Example
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-------
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SoC common .dtsi file:
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canfd: can@e66c0000 {
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compatible = "renesas,r8a7795-canfd",
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"renesas,rcar-gen3-canfd";
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reg = <0 0xe66c0000 0 0x8000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 914>,
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<&cpg CPG_CORE R8A7795_CLK_CANFD>,
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<&can_clk>;
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clock-names = "fck", "canfd", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
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assigned-clock-rates = <40000000>;
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power-domains = <&cpg>;
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status = "disabled";
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channel0 {
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status = "disabled";
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};
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channel1 {
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status = "disabled";
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};
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};
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Board specific .dts file:
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E.g. below enables Channel 1 alone in the board in Classical CAN only mode.
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&canfd {
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pinctrl-0 = <&canfd1_pins>;
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pinctrl-names = "default";
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renesas,no-can-fd;
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status = "okay";
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channel1 {
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status = "okay";
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};
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};
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E.g. below enables Channel 0 alone in the board using External clock
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as fCAN clock.
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&canfd {
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pinctrl-0 = <&canfd0_pins>, <&can_clk_pins>;
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pinctrl-names = "default";
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status = "okay";
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channel0 {
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status = "okay";
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};
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};
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139
Documentation/devicetree/bindings/net/can/renesas,rcar-can.yaml
Normal file
139
Documentation/devicetree/bindings/net/can/renesas,rcar-can.yaml
Normal file
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@ -0,0 +1,139 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas R-Car CAN Controller
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maintainers:
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- Sergei Shtylyov <sergei.shtylyov@gmail.com>
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,can-r8a7778 # R-Car M1-A
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- renesas,can-r8a7779 # R-Car H1
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- const: renesas,rcar-gen1-can # R-Car Gen1
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- items:
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- enum:
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- renesas,can-r8a7742 # RZ/G1H
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- renesas,can-r8a7743 # RZ/G1M
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- renesas,can-r8a7744 # RZ/G1N
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- renesas,can-r8a7745 # RZ/G1E
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- renesas,can-r8a77470 # RZ/G1C
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- renesas,can-r8a7790 # R-Car H2
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- renesas,can-r8a7791 # R-Car M2-W
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- renesas,can-r8a7792 # R-Car V2H
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- renesas,can-r8a7793 # R-Car M2-N
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- renesas,can-r8a7794 # R-Car E2
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- const: renesas,rcar-gen2-can # R-Car Gen2 and RZ/G1
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- items:
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- enum:
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- renesas,can-r8a774a1 # RZ/G2M
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- renesas,can-r8a774b1 # RZ/G2N
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- renesas,can-r8a774c0 # RZ/G2E
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- renesas,can-r8a774e1 # RZ/G2H
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- renesas,can-r8a7795 # R-Car H3
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- renesas,can-r8a7796 # R-Car M3-W
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- renesas,can-r8a77961 # R-Car M3-W+
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- renesas,can-r8a77965 # R-Car M3-N
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- renesas,can-r8a77990 # R-Car E3
|
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- renesas,can-r8a77995 # R-Car D3
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- const: renesas,rcar-gen3-can # R-Car Gen3 and RZ/G2
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 3
|
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clock-names:
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items:
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- const: clkp1
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- const: clkp2
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- const: can_clk
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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renesas,can-clock-select:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1, 3 ]
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default: 0
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description: |
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R-Car CAN Clock Source Select. Valid values are:
|
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<0x0> (default) : Peripheral clock (clkp1)
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<0x1> : Peripheral clock (clkp2)
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<0x3> : External input clock
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assigned-clocks:
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description:
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Reference to the clkp2 (CANFD) clock.
|
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On R-Car Gen3 and RZ/G2 SoCs, "clkp2" is the CANFD clock. This is a div6
|
||||
clock and can be used by both CAN and CAN FD controllers at the same
|
||||
time. It needs to be scaled to maximum frequency if any of these
|
||||
controllers use it.
|
||||
|
||||
assigned-clock-rates:
|
||||
description: Maximum frequency of the CANFD clock.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: can-controller.yaml#
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,rcar-gen1-can
|
||||
then:
|
||||
required:
|
||||
- resets
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,rcar-gen3-can
|
||||
then:
|
||||
required:
|
||||
- assigned-clocks
|
||||
- assigned-clock-rates
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7791-sysc.h>
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
|
||||
reg = <0xe6e80000 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 916>,
|
||||
<&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
};
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car CAN FD Controller
|
||||
|
||||
maintainers:
|
||||
- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
|
||||
|
||||
allOf:
|
||||
- $ref: can-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r8a774a1-canfd # RZ/G2M
|
||||
- renesas,r8a774b1-canfd # RZ/G2N
|
||||
- renesas,r8a774c0-canfd # RZ/G2E
|
||||
- renesas,r8a774e1-canfd # RZ/G2H
|
||||
- renesas,r8a7795-canfd # R-Car H3
|
||||
- renesas,r8a7796-canfd # R-Car M3-W
|
||||
- renesas,r8a77965-canfd # R-Car M3-N
|
||||
- renesas,r8a77970-canfd # R-Car V3M
|
||||
- renesas,r8a77980-canfd # R-Car V3H
|
||||
- renesas,r8a77990-canfd # R-Car E3
|
||||
- renesas,r8a77995-canfd # R-Car D3
|
||||
- const: renesas,rcar-gen3-canfd # R-Car Gen3 and RZ/G2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: Channel interrupt
|
||||
- description: Global interrupt
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fck
|
||||
- const: canfd
|
||||
- const: can_clk
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
renesas,no-can-fd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The controller can operate in either CAN FD only mode (default) or
|
||||
Classical CAN only mode. The mode is global to both the channels.
|
||||
Specify this property to put the controller in Classical CAN only mode.
|
||||
|
||||
assigned-clocks:
|
||||
description:
|
||||
Reference to the CANFD clock. The CANFD clock is a div6 clock and can be
|
||||
used by both CAN (if present) and CAN FD controllers at the same time.
|
||||
It needs to be scaled to maximum frequency if any of these controllers
|
||||
use it.
|
||||
|
||||
assigned-clock-rates:
|
||||
description: Maximum frequency of the CANFD clock.
|
||||
|
||||
patternProperties:
|
||||
"^channel[01]$":
|
||||
type: object
|
||||
description:
|
||||
The controller supports two channels and each is represented as a child
|
||||
node. Each child node supports the "status" property only, which
|
||||
is used to enable/disable the respective channel.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
- resets
|
||||
- assigned-clocks
|
||||
- assigned-clock-rates
|
||||
- channel0
|
||||
- channel1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7795-sysc.h>
|
||||
|
||||
canfd: can@e66c0000 {
|
||||
compatible = "renesas,r8a7795-canfd",
|
||||
"renesas,rcar-gen3-canfd";
|
||||
reg = <0xe66c0000 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "fck", "canfd", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 914>;
|
||||
|
||||
channel0 {
|
||||
};
|
||||
|
||||
channel1 {
|
||||
};
|
||||
};
|
||||
|
|
@ -169,7 +169,7 @@ static const struct can_bittiming_const at91_bittiming_const = {
|
|||
};
|
||||
|
||||
#define AT91_IS(_model) \
|
||||
static inline int at91_is_sam##_model(const struct at91_priv *priv) \
|
||||
static inline int __maybe_unused at91_is_sam##_model(const struct at91_priv *priv) \
|
||||
{ \
|
||||
return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,5 +4,10 @@
|
|||
#
|
||||
|
||||
obj-$(CONFIG_CAN_C_CAN) += c_can.o
|
||||
|
||||
c_can-objs :=
|
||||
c_can-objs += c_can_ethtool.o
|
||||
c_can-objs += c_can_main.o
|
||||
|
||||
obj-$(CONFIG_CAN_C_CAN_PLATFORM) += c_can_platform.o
|
||||
obj-$(CONFIG_CAN_C_CAN_PCI) += c_can_pci.o
|
||||
|
|
|
|||
|
|
@ -205,7 +205,6 @@ struct c_can_priv {
|
|||
struct c_can_raminit raminit_sys; /* RAMINIT via syscon regmap */
|
||||
void (*raminit)(const struct c_can_priv *priv, bool enable);
|
||||
u32 comm_rcv_high;
|
||||
u32 rxmasked;
|
||||
u32 dlc[];
|
||||
};
|
||||
|
||||
|
|
@ -219,4 +218,6 @@ int c_can_power_up(struct net_device *dev);
|
|||
int c_can_power_down(struct net_device *dev);
|
||||
#endif
|
||||
|
||||
void c_can_set_ethtool_ops(struct net_device *dev);
|
||||
|
||||
#endif /* C_CAN_H */
|
||||
|
|
|
|||
43
drivers/net/can/c_can/c_can_ethtool.c
Normal file
43
drivers/net/can/c_can/c_can_ethtool.c
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright 2021, Dario Binacchi <dariobin@libero.it>
|
||||
*/
|
||||
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/can/dev.h>
|
||||
|
||||
#include "c_can.h"
|
||||
|
||||
static void c_can_get_drvinfo(struct net_device *netdev,
|
||||
struct ethtool_drvinfo *info)
|
||||
{
|
||||
struct c_can_priv *priv = netdev_priv(netdev);
|
||||
struct platform_device *pdev = to_platform_device(priv->device);
|
||||
|
||||
strscpy(info->driver, "c_can", sizeof(info->driver));
|
||||
strscpy(info->bus_info, pdev->name, sizeof(info->bus_info));
|
||||
}
|
||||
|
||||
static void c_can_get_ringparam(struct net_device *netdev,
|
||||
struct ethtool_ringparam *ring)
|
||||
{
|
||||
struct c_can_priv *priv = netdev_priv(netdev);
|
||||
|
||||
ring->rx_max_pending = priv->msg_obj_num;
|
||||
ring->tx_max_pending = priv->msg_obj_num;
|
||||
ring->rx_pending = priv->msg_obj_rx_num;
|
||||
ring->tx_pending = priv->msg_obj_tx_num;
|
||||
}
|
||||
|
||||
static const struct ethtool_ops c_can_ethtool_ops = {
|
||||
.get_drvinfo = c_can_get_drvinfo,
|
||||
.get_ringparam = c_can_get_ringparam,
|
||||
};
|
||||
|
||||
void c_can_set_ethtool_ops(struct net_device *netdev)
|
||||
{
|
||||
netdev->ethtool_ops = &c_can_ethtool_ops;
|
||||
}
|
||||
|
|
@ -599,7 +599,6 @@ static int c_can_chip_config(struct net_device *dev)
|
|||
|
||||
/* Clear all internal status */
|
||||
atomic_set(&priv->tx_active, 0);
|
||||
priv->rxmasked = 0;
|
||||
priv->tx_dir = 0;
|
||||
|
||||
/* set bittiming params */
|
||||
|
|
@ -1335,6 +1334,7 @@ int register_c_can_dev(struct net_device *dev)
|
|||
|
||||
dev->flags |= IFF_ECHO; /* we support local echo */
|
||||
dev->netdev_ops = &c_can_netdev_ops;
|
||||
c_can_set_ethtool_ops(dev);
|
||||
|
||||
err = register_candev(dev);
|
||||
if (!err)
|
||||
|
|
@ -83,44 +83,25 @@ enum m_can_reg {
|
|||
#define MRAM_CFG_LEN 8
|
||||
|
||||
/* Core Release Register (CREL) */
|
||||
#define CREL_REL_SHIFT 28
|
||||
#define CREL_REL_MASK (0xF << CREL_REL_SHIFT)
|
||||
#define CREL_STEP_SHIFT 24
|
||||
#define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT)
|
||||
#define CREL_SUBSTEP_SHIFT 20
|
||||
#define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT)
|
||||
#define CREL_REL_MASK GENMASK(31, 28)
|
||||
#define CREL_STEP_MASK GENMASK(27, 24)
|
||||
#define CREL_SUBSTEP_MASK GENMASK(23, 20)
|
||||
|
||||
/* Data Bit Timing & Prescaler Register (DBTP) */
|
||||
#define DBTP_TDC BIT(23)
|
||||
#define DBTP_DBRP_SHIFT 16
|
||||
#define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT)
|
||||
#define DBTP_DTSEG1_SHIFT 8
|
||||
#define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT)
|
||||
#define DBTP_DTSEG2_SHIFT 4
|
||||
#define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT)
|
||||
#define DBTP_DSJW_SHIFT 0
|
||||
#define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT)
|
||||
#define DBTP_DBRP_MASK GENMASK(20, 16)
|
||||
#define DBTP_DTSEG1_MASK GENMASK(12, 8)
|
||||
#define DBTP_DTSEG2_MASK GENMASK(7, 4)
|
||||
#define DBTP_DSJW_MASK GENMASK(3, 0)
|
||||
|
||||
/* Transmitter Delay Compensation Register (TDCR) */
|
||||
#define TDCR_TDCO_SHIFT 8
|
||||
#define TDCR_TDCO_MASK (0x7F << TDCR_TDCO_SHIFT)
|
||||
#define TDCR_TDCF_SHIFT 0
|
||||
#define TDCR_TDCF_MASK (0x7F << TDCR_TDCF_SHIFT)
|
||||
#define TDCR_TDCO_MASK GENMASK(14, 8)
|
||||
#define TDCR_TDCF_MASK GENMASK(6, 0)
|
||||
|
||||
/* Test Register (TEST) */
|
||||
#define TEST_LBCK BIT(4)
|
||||
|
||||
/* CC Control Register(CCCR) */
|
||||
#define CCCR_CMR_MASK 0x3
|
||||
#define CCCR_CMR_SHIFT 10
|
||||
#define CCCR_CMR_CANFD 0x1
|
||||
#define CCCR_CMR_CANFD_BRS 0x2
|
||||
#define CCCR_CMR_CAN 0x3
|
||||
#define CCCR_CME_MASK 0x3
|
||||
#define CCCR_CME_SHIFT 8
|
||||
#define CCCR_CME_CAN 0
|
||||
#define CCCR_CME_CANFD 0x1
|
||||
#define CCCR_CME_CANFD_BRS 0x2
|
||||
/* CC Control Register (CCCR) */
|
||||
#define CCCR_TXP BIT(14)
|
||||
#define CCCR_TEST BIT(7)
|
||||
#define CCCR_DAR BIT(6)
|
||||
|
|
@ -130,24 +111,31 @@ enum m_can_reg {
|
|||
#define CCCR_ASM BIT(2)
|
||||
#define CCCR_CCE BIT(1)
|
||||
#define CCCR_INIT BIT(0)
|
||||
#define CCCR_CANFD 0x10
|
||||
/* for version 3.0.x */
|
||||
#define CCCR_CMR_MASK GENMASK(11, 10)
|
||||
#define CCCR_CMR_CANFD 0x1
|
||||
#define CCCR_CMR_CANFD_BRS 0x2
|
||||
#define CCCR_CMR_CAN 0x3
|
||||
#define CCCR_CME_MASK GENMASK(9, 8)
|
||||
#define CCCR_CME_CAN 0
|
||||
#define CCCR_CME_CANFD 0x1
|
||||
#define CCCR_CME_CANFD_BRS 0x2
|
||||
/* for version >=3.1.x */
|
||||
#define CCCR_EFBI BIT(13)
|
||||
#define CCCR_PXHD BIT(12)
|
||||
#define CCCR_BRSE BIT(9)
|
||||
#define CCCR_FDOE BIT(8)
|
||||
/* only for version >=3.2.x */
|
||||
/* for version >=3.2.x */
|
||||
#define CCCR_NISO BIT(15)
|
||||
/* for version >=3.3.x */
|
||||
#define CCCR_WMM BIT(11)
|
||||
#define CCCR_UTSU BIT(10)
|
||||
|
||||
/* Nominal Bit Timing & Prescaler Register (NBTP) */
|
||||
#define NBTP_NSJW_SHIFT 25
|
||||
#define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT)
|
||||
#define NBTP_NBRP_SHIFT 16
|
||||
#define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT)
|
||||
#define NBTP_NTSEG1_SHIFT 8
|
||||
#define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT)
|
||||
#define NBTP_NTSEG2_SHIFT 0
|
||||
#define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT)
|
||||
#define NBTP_NSJW_MASK GENMASK(31, 25)
|
||||
#define NBTP_NBRP_MASK GENMASK(24, 16)
|
||||
#define NBTP_NTSEG1_MASK GENMASK(15, 8)
|
||||
#define NBTP_NTSEG2_MASK GENMASK(6, 0)
|
||||
|
||||
/* Timestamp Counter Configuration Register (TSCC) */
|
||||
#define TSCC_TCP_MASK GENMASK(19, 16)
|
||||
|
|
@ -159,20 +147,18 @@ enum m_can_reg {
|
|||
/* Timestamp Counter Value Register (TSCV) */
|
||||
#define TSCV_TSC_MASK GENMASK(15, 0)
|
||||
|
||||
/* Error Counter Register(ECR) */
|
||||
/* Error Counter Register (ECR) */
|
||||
#define ECR_RP BIT(15)
|
||||
#define ECR_REC_SHIFT 8
|
||||
#define ECR_REC_MASK (0x7f << ECR_REC_SHIFT)
|
||||
#define ECR_TEC_SHIFT 0
|
||||
#define ECR_TEC_MASK 0xff
|
||||
#define ECR_REC_MASK GENMASK(14, 8)
|
||||
#define ECR_TEC_MASK GENMASK(7, 0)
|
||||
|
||||
/* Protocol Status Register(PSR) */
|
||||
/* Protocol Status Register (PSR) */
|
||||
#define PSR_BO BIT(7)
|
||||
#define PSR_EW BIT(6)
|
||||
#define PSR_EP BIT(5)
|
||||
#define PSR_LEC_MASK 0x7
|
||||
#define PSR_LEC_MASK GENMASK(2, 0)
|
||||
|
||||
/* Interrupt Register(IR) */
|
||||
/* Interrupt Register (IR) */
|
||||
#define IR_ALL_INT 0xffffffff
|
||||
|
||||
/* Renamed bits for versions > 3.1.x */
|
||||
|
|
@ -221,6 +207,7 @@ enum m_can_reg {
|
|||
IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
|
||||
IR_RF1L | IR_RF0L)
|
||||
#define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
|
||||
|
||||
/* Interrupts for version >= 3.1.x */
|
||||
#define IR_ERR_LEC_31X (IR_PED | IR_PEA)
|
||||
#define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \
|
||||
|
|
@ -237,58 +224,47 @@ enum m_can_reg {
|
|||
#define ILE_EINT0 BIT(0)
|
||||
|
||||
/* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
|
||||
#define RXFC_FWM_SHIFT 24
|
||||
#define RXFC_FWM_MASK (0x7f << RXFC_FWM_SHIFT)
|
||||
#define RXFC_FS_SHIFT 16
|
||||
#define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT)
|
||||
#define RXFC_FWM_MASK GENMASK(30, 24)
|
||||
#define RXFC_FS_MASK GENMASK(22, 16)
|
||||
|
||||
/* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
|
||||
#define RXFS_RFL BIT(25)
|
||||
#define RXFS_FF BIT(24)
|
||||
#define RXFS_FPI_SHIFT 16
|
||||
#define RXFS_FPI_MASK 0x3f0000
|
||||
#define RXFS_FGI_SHIFT 8
|
||||
#define RXFS_FGI_MASK 0x3f00
|
||||
#define RXFS_FFL_MASK 0x7f
|
||||
#define RXFS_FPI_MASK GENMASK(21, 16)
|
||||
#define RXFS_FGI_MASK GENMASK(13, 8)
|
||||
#define RXFS_FFL_MASK GENMASK(6, 0)
|
||||
|
||||
/* Rx Buffer / FIFO Element Size Configuration (RXESC) */
|
||||
#define M_CAN_RXESC_8BYTES 0x0
|
||||
#define M_CAN_RXESC_64BYTES 0x777
|
||||
#define RXESC_RBDS_MASK GENMASK(10, 8)
|
||||
#define RXESC_F1DS_MASK GENMASK(6, 4)
|
||||
#define RXESC_F0DS_MASK GENMASK(2, 0)
|
||||
#define RXESC_64B 0x7
|
||||
|
||||
/* Tx Buffer Configuration(TXBC) */
|
||||
#define TXBC_NDTB_SHIFT 16
|
||||
#define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT)
|
||||
#define TXBC_TFQS_SHIFT 24
|
||||
#define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT)
|
||||
/* Tx Buffer Configuration (TXBC) */
|
||||
#define TXBC_TFQS_MASK GENMASK(29, 24)
|
||||
#define TXBC_NDTB_MASK GENMASK(21, 16)
|
||||
|
||||
/* Tx FIFO/Queue Status (TXFQS) */
|
||||
#define TXFQS_TFQF BIT(21)
|
||||
#define TXFQS_TFQPI_SHIFT 16
|
||||
#define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT)
|
||||
#define TXFQS_TFGI_SHIFT 8
|
||||
#define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT)
|
||||
#define TXFQS_TFFL_SHIFT 0
|
||||
#define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT)
|
||||
#define TXFQS_TFQPI_MASK GENMASK(20, 16)
|
||||
#define TXFQS_TFGI_MASK GENMASK(12, 8)
|
||||
#define TXFQS_TFFL_MASK GENMASK(5, 0)
|
||||
|
||||
/* Tx Buffer Element Size Configuration(TXESC) */
|
||||
#define TXESC_TBDS_8BYTES 0x0
|
||||
#define TXESC_TBDS_64BYTES 0x7
|
||||
/* Tx Buffer Element Size Configuration (TXESC) */
|
||||
#define TXESC_TBDS_MASK GENMASK(2, 0)
|
||||
#define TXESC_TBDS_64B 0x7
|
||||
|
||||
/* Tx Event FIFO Configuration (TXEFC) */
|
||||
#define TXEFC_EFS_SHIFT 16
|
||||
#define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT)
|
||||
#define TXEFC_EFS_MASK GENMASK(21, 16)
|
||||
|
||||
/* Tx Event FIFO Status (TXEFS) */
|
||||
#define TXEFS_TEFL BIT(25)
|
||||
#define TXEFS_EFF BIT(24)
|
||||
#define TXEFS_EFGI_SHIFT 8
|
||||
#define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT)
|
||||
#define TXEFS_EFFL_SHIFT 0
|
||||
#define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT)
|
||||
#define TXEFS_EFGI_MASK GENMASK(12, 8)
|
||||
#define TXEFS_EFFL_MASK GENMASK(5, 0)
|
||||
|
||||
/* Tx Event FIFO Acknowledge (TXEFA) */
|
||||
#define TXEFA_EFAI_SHIFT 0
|
||||
#define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT)
|
||||
#define TXEFA_EFAI_MASK GENMASK(4, 0)
|
||||
|
||||
/* Message RAM Configuration (in bytes) */
|
||||
#define SIDF_ELEMENT_SIZE 4
|
||||
|
|
@ -324,13 +300,12 @@ enum m_can_reg {
|
|||
#define TX_BUF_EFC BIT(23)
|
||||
#define TX_BUF_FDF BIT(21)
|
||||
#define TX_BUF_BRS BIT(20)
|
||||
#define TX_BUF_MM_SHIFT 24
|
||||
#define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
|
||||
#define TX_BUF_MM_MASK GENMASK(31, 24)
|
||||
#define TX_BUF_DLC_MASK GENMASK(19, 16)
|
||||
|
||||
/* Tx event FIFO Element */
|
||||
/* E1 */
|
||||
#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
|
||||
#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
|
||||
#define TX_EVENT_MM_MASK GENMASK(31, 24)
|
||||
#define TX_EVENT_TXTS_MASK GENMASK(15, 0)
|
||||
|
||||
static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg)
|
||||
|
|
@ -449,8 +424,8 @@ static void m_can_clean(struct net_device *net)
|
|||
|
||||
net->stats.tx_errors++;
|
||||
if (cdev->version > 30)
|
||||
putidx = ((m_can_read(cdev, M_CAN_TXFQS) &
|
||||
TXFQS_TFQPI_MASK) >> TXFQS_TFQPI_SHIFT);
|
||||
putidx = FIELD_GET(TXFQS_TFQPI_MASK,
|
||||
m_can_read(cdev, M_CAN_TXFQS));
|
||||
|
||||
can_free_echo_skb(cdev->net, putidx, NULL);
|
||||
cdev->tx_skb = NULL;
|
||||
|
|
@ -490,7 +465,7 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
|
|||
int i;
|
||||
|
||||
/* calculate the fifo get index for where to read data */
|
||||
fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT;
|
||||
fgi = FIELD_GET(RXFS_FGI_MASK, rxfs);
|
||||
dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC);
|
||||
if (dlc & RX_BUF_FDF)
|
||||
skb = alloc_canfd_skb(dev, &cf);
|
||||
|
|
@ -663,8 +638,8 @@ static int __m_can_get_berr_counter(const struct net_device *dev,
|
|||
unsigned int ecr;
|
||||
|
||||
ecr = m_can_read(cdev, M_CAN_ECR);
|
||||
bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
|
||||
bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT;
|
||||
bec->rxerr = FIELD_GET(ECR_REC_MASK, ecr);
|
||||
bec->txerr = FIELD_GET(ECR_TEC_MASK, ecr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1004,24 +979,23 @@ static void m_can_echo_tx_event(struct net_device *dev)
|
|||
m_can_txefs = m_can_read(cdev, M_CAN_TXEFS);
|
||||
|
||||
/* Get Tx Event fifo element count */
|
||||
txe_count = (m_can_txefs & TXEFS_EFFL_MASK) >> TXEFS_EFFL_SHIFT;
|
||||
txe_count = FIELD_GET(TXEFS_EFFL_MASK, m_can_txefs);
|
||||
|
||||
/* Get and process all sent elements */
|
||||
for (i = 0; i < txe_count; i++) {
|
||||
u32 txe, timestamp = 0;
|
||||
|
||||
/* retrieve get index */
|
||||
fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK) >>
|
||||
TXEFS_EFGI_SHIFT;
|
||||
fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_read(cdev, M_CAN_TXEFS));
|
||||
|
||||
/* get message marker, timestamp */
|
||||
txe = m_can_txe_fifo_read(cdev, fgi, 4);
|
||||
msg_mark = (txe & TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
|
||||
msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe);
|
||||
timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe);
|
||||
|
||||
/* ack txe element */
|
||||
m_can_write(cdev, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
|
||||
(fgi << TXEFA_EFAI_SHIFT)));
|
||||
m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK,
|
||||
fgi));
|
||||
|
||||
/* update stats */
|
||||
m_can_tx_update_stats(cdev, msg_mark, timestamp);
|
||||
|
|
@ -1147,8 +1121,10 @@ static int m_can_set_bittiming(struct net_device *dev)
|
|||
sjw = bt->sjw - 1;
|
||||
tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
|
||||
tseg2 = bt->phase_seg2 - 1;
|
||||
reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) |
|
||||
(tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT);
|
||||
reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) |
|
||||
FIELD_PREP(NBTP_NSJW_MASK, sjw) |
|
||||
FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) |
|
||||
FIELD_PREP(NBTP_NTSEG2_MASK, tseg2);
|
||||
m_can_write(cdev, M_CAN_NBTP, reg_btp);
|
||||
|
||||
if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
|
||||
|
|
@ -1185,13 +1161,13 @@ static int m_can_set_bittiming(struct net_device *dev)
|
|||
|
||||
reg_btp |= DBTP_TDC;
|
||||
m_can_write(cdev, M_CAN_TDCR,
|
||||
tdco << TDCR_TDCO_SHIFT);
|
||||
FIELD_PREP(TDCR_TDCO_MASK, tdco));
|
||||
}
|
||||
|
||||
reg_btp |= (brp << DBTP_DBRP_SHIFT) |
|
||||
(sjw << DBTP_DSJW_SHIFT) |
|
||||
(tseg1 << DBTP_DTSEG1_SHIFT) |
|
||||
(tseg2 << DBTP_DTSEG2_SHIFT);
|
||||
reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) |
|
||||
FIELD_PREP(NBTP_NSJW_MASK, sjw) |
|
||||
FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) |
|
||||
FIELD_PREP(NBTP_NTSEG2_MASK, tseg2);
|
||||
|
||||
m_can_write(cdev, M_CAN_DBTP, reg_btp);
|
||||
}
|
||||
|
|
@ -1217,44 +1193,50 @@ static void m_can_chip_config(struct net_device *dev)
|
|||
m_can_config_endisable(cdev, true);
|
||||
|
||||
/* RX Buffer/FIFO Element Size 64 bytes data field */
|
||||
m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES);
|
||||
m_can_write(cdev, M_CAN_RXESC,
|
||||
FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) |
|
||||
FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) |
|
||||
FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B));
|
||||
|
||||
/* Accept Non-matching Frames Into FIFO 0 */
|
||||
m_can_write(cdev, M_CAN_GFC, 0x0);
|
||||
|
||||
if (cdev->version == 30) {
|
||||
/* only support one Tx Buffer currently */
|
||||
m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
|
||||
m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) |
|
||||
cdev->mcfg[MRAM_TXB].off);
|
||||
} else {
|
||||
/* TX FIFO is used for newer IP Core versions */
|
||||
m_can_write(cdev, M_CAN_TXBC,
|
||||
(cdev->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) |
|
||||
(cdev->mcfg[MRAM_TXB].off));
|
||||
FIELD_PREP(TXBC_TFQS_MASK,
|
||||
cdev->mcfg[MRAM_TXB].num) |
|
||||
cdev->mcfg[MRAM_TXB].off);
|
||||
}
|
||||
|
||||
/* support 64 bytes payload */
|
||||
m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES);
|
||||
m_can_write(cdev, M_CAN_TXESC,
|
||||
FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B));
|
||||
|
||||
/* TX Event FIFO */
|
||||
if (cdev->version == 30) {
|
||||
m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
|
||||
m_can_write(cdev, M_CAN_TXEFC,
|
||||
FIELD_PREP(TXEFC_EFS_MASK, 1) |
|
||||
cdev->mcfg[MRAM_TXE].off);
|
||||
} else {
|
||||
/* Full TX Event FIFO is used */
|
||||
m_can_write(cdev, M_CAN_TXEFC,
|
||||
((cdev->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT)
|
||||
& TXEFC_EFS_MASK) |
|
||||
FIELD_PREP(TXEFC_EFS_MASK,
|
||||
cdev->mcfg[MRAM_TXE].num) |
|
||||
cdev->mcfg[MRAM_TXE].off);
|
||||
}
|
||||
|
||||
/* rx fifo configuration, blocking mode, fifo size 1 */
|
||||
m_can_write(cdev, M_CAN_RXF0C,
|
||||
(cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) |
|
||||
FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) |
|
||||
cdev->mcfg[MRAM_RXF0].off);
|
||||
|
||||
m_can_write(cdev, M_CAN_RXF1C,
|
||||
(cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) |
|
||||
FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) |
|
||||
cdev->mcfg[MRAM_RXF1].off);
|
||||
|
||||
cccr = m_can_read(cdev, M_CAN_CCCR);
|
||||
|
|
@ -1264,11 +1246,11 @@ static void m_can_chip_config(struct net_device *dev)
|
|||
/* Version 3.0.x */
|
||||
|
||||
cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR |
|
||||
(CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
|
||||
(CCCR_CME_MASK << CCCR_CME_SHIFT));
|
||||
FIELD_PREP(CCCR_CMR_MASK, FIELD_MAX(CCCR_CMR_MASK)) |
|
||||
FIELD_PREP(CCCR_CME_MASK, FIELD_MAX(CCCR_CME_MASK)));
|
||||
|
||||
if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
|
||||
cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
|
||||
cccr |= FIELD_PREP(CCCR_CME_MASK, CCCR_CME_CANFD_BRS);
|
||||
|
||||
} else {
|
||||
/* Version 3.1.x or 3.2.x */
|
||||
|
|
@ -1372,8 +1354,8 @@ static int m_can_check_core_release(struct m_can_classdev *cdev)
|
|||
* Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
|
||||
*/
|
||||
crel_reg = m_can_read(cdev, M_CAN_CREL);
|
||||
rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT);
|
||||
step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT);
|
||||
rel = (u8)FIELD_GET(CREL_REL_MASK, crel_reg);
|
||||
step = (u8)FIELD_GET(CREL_STEP_MASK, crel_reg);
|
||||
|
||||
if (rel == 3) {
|
||||
/* M_CAN v3.x.y: create return value */
|
||||
|
|
@ -1593,16 +1575,16 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
|
|||
|
||||
if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
|
||||
cccr = m_can_read(cdev, M_CAN_CCCR);
|
||||
cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
|
||||
cccr &= ~CCCR_CMR_MASK;
|
||||
if (can_is_canfd_skb(skb)) {
|
||||
if (cf->flags & CANFD_BRS)
|
||||
cccr |= CCCR_CMR_CANFD_BRS <<
|
||||
CCCR_CMR_SHIFT;
|
||||
cccr |= FIELD_PREP(CCCR_CMR_MASK,
|
||||
CCCR_CMR_CANFD_BRS);
|
||||
else
|
||||
cccr |= CCCR_CMR_CANFD <<
|
||||
CCCR_CMR_SHIFT;
|
||||
cccr |= FIELD_PREP(CCCR_CMR_MASK,
|
||||
CCCR_CMR_CANFD);
|
||||
} else {
|
||||
cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
|
||||
cccr |= FIELD_PREP(CCCR_CMR_MASK, CCCR_CMR_CAN);
|
||||
}
|
||||
m_can_write(cdev, M_CAN_CCCR, cccr);
|
||||
}
|
||||
|
|
@ -1629,8 +1611,8 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
|
|||
}
|
||||
|
||||
/* get put index for frame */
|
||||
putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
|
||||
>> TXFQS_TFQPI_SHIFT);
|
||||
putidx = FIELD_GET(TXFQS_TFQPI_MASK,
|
||||
m_can_read(cdev, M_CAN_TXFQS));
|
||||
/* Write ID Field to FIFO Element */
|
||||
m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id);
|
||||
|
||||
|
|
@ -1648,9 +1630,9 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
|
|||
* sending the correct echo frame
|
||||
*/
|
||||
m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC,
|
||||
((putidx << TX_BUF_MM_SHIFT) &
|
||||
TX_BUF_MM_MASK) |
|
||||
(can_fd_len2dlc(cf->len) << 16) |
|
||||
FIELD_PREP(TX_BUF_MM_MASK, putidx) |
|
||||
FIELD_PREP(TX_BUF_DLC_MASK,
|
||||
can_fd_len2dlc(cf->len)) |
|
||||
fdflags | TX_BUF_EFC);
|
||||
|
||||
for (i = 0; i < cf->len; i += 4)
|
||||
|
|
@ -1810,11 +1792,11 @@ static void m_can_of_parse_mram(struct m_can_classdev *cdev,
|
|||
cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off +
|
||||
cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
|
||||
cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
|
||||
(RXFC_FS_MASK >> RXFC_FS_SHIFT);
|
||||
FIELD_MAX(RXFC_FS_MASK);
|
||||
cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off +
|
||||
cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
|
||||
cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
|
||||
(RXFC_FS_MASK >> RXFC_FS_SHIFT);
|
||||
FIELD_MAX(RXFC_FS_MASK);
|
||||
cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off +
|
||||
cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
|
||||
cdev->mcfg[MRAM_RXB].num = mram_config_vals[5];
|
||||
|
|
@ -1824,7 +1806,7 @@ static void m_can_of_parse_mram(struct m_can_classdev *cdev,
|
|||
cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off +
|
||||
cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
|
||||
cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] &
|
||||
(TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
|
||||
FIELD_MAX(TXBC_NDTB_MASK);
|
||||
|
||||
dev_dbg(cdev->dev,
|
||||
"sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
|
||||
|
|
|
|||
|
|
@ -239,7 +239,6 @@ static int softing_handle_1(struct softing *card)
|
|||
DPRAM_INFO_BUSSTATE2 : DPRAM_INFO_BUSSTATE]);
|
||||
/* timestamp */
|
||||
tmp_u32 = le32_to_cpup((void *)ptr);
|
||||
ptr += 4;
|
||||
ktime = softing_raw2ktime(card, tmp_u32);
|
||||
|
||||
++netdev->stats.rx_errors;
|
||||
|
|
@ -276,7 +275,6 @@ static int softing_handle_1(struct softing *card)
|
|||
ktime = softing_raw2ktime(card, tmp_u32);
|
||||
if (!(msg.can_id & CAN_RTR_FLAG))
|
||||
memcpy(&msg.data[0], ptr, 8);
|
||||
ptr += 8;
|
||||
/* update socket */
|
||||
if (cmd & CMD_ACK) {
|
||||
/* acknowledge, was tx msg */
|
||||
|
|
|
|||
|
|
@ -871,7 +871,7 @@ static int hi3110_can_probe(struct spi_device *spi)
|
|||
CAN_CTRLMODE_BERR_REPORTING;
|
||||
|
||||
if (of_id)
|
||||
priv->model = (enum hi3110_model)of_id->data;
|
||||
priv->model = (enum hi3110_model)(uintptr_t)of_id->data;
|
||||
else
|
||||
priv->model = spi_get_device_id(spi)->driver_data;
|
||||
priv->net = net;
|
||||
|
|
|
|||
|
|
@ -1330,7 +1330,7 @@ static int mcp251x_can_probe(struct spi_device *spi)
|
|||
priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
|
||||
CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
|
||||
if (match)
|
||||
priv->model = (enum mcp251x_model)match;
|
||||
priv->model = (enum mcp251x_model)(uintptr_t)match;
|
||||
else
|
||||
priv->model = spi_get_device_id(spi)->driver_data;
|
||||
priv->net = net;
|
||||
|
|
|
|||
|
|
@ -560,7 +560,7 @@ mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
|
|||
return __mcp251xfd_chip_set_mode(priv, mode_req, false);
|
||||
}
|
||||
|
||||
static inline int
|
||||
static inline int __maybe_unused
|
||||
mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv,
|
||||
const u8 mode_req)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -76,7 +76,9 @@ config CAN_KVASER_USB
|
|||
- Scania VCI2 (if you have the Kvaser logo on top)
|
||||
- Kvaser BlackBird v2
|
||||
- Kvaser Leaf Pro HS v2
|
||||
- Kvaser Hybrid CAN/LIN
|
||||
- Kvaser Hybrid 2xCAN/LIN
|
||||
- Kvaser Hybrid Pro CAN/LIN
|
||||
- Kvaser Hybrid Pro 2xCAN/LIN
|
||||
- Kvaser Memorator 2xHS v2
|
||||
- Kvaser Memorator Pro 2xHS v2
|
||||
|
|
|
|||
|
|
@ -79,16 +79,18 @@
|
|||
#define USB_USBCAN_PRO_2HS_V2_PRODUCT_ID 264
|
||||
#define USB_MEMO_2HS_PRODUCT_ID 265
|
||||
#define USB_MEMO_PRO_2HS_V2_PRODUCT_ID 266
|
||||
#define USB_HYBRID_CANLIN_PRODUCT_ID 267
|
||||
#define USB_HYBRID_2CANLIN_PRODUCT_ID 267
|
||||
#define USB_ATI_USBCAN_PRO_2HS_V2_PRODUCT_ID 268
|
||||
#define USB_ATI_MEMO_PRO_2HS_V2_PRODUCT_ID 269
|
||||
#define USB_HYBRID_PRO_CANLIN_PRODUCT_ID 270
|
||||
#define USB_HYBRID_PRO_2CANLIN_PRODUCT_ID 270
|
||||
#define USB_U100_PRODUCT_ID 273
|
||||
#define USB_U100P_PRODUCT_ID 274
|
||||
#define USB_U100S_PRODUCT_ID 275
|
||||
#define USB_USBCAN_PRO_4HS_PRODUCT_ID 276
|
||||
#define USB_HYBRID_CANLIN_PRODUCT_ID 277
|
||||
#define USB_HYBRID_PRO_CANLIN_PRODUCT_ID 278
|
||||
#define USB_HYDRA_PRODUCT_ID_END \
|
||||
USB_USBCAN_PRO_4HS_PRODUCT_ID
|
||||
USB_HYBRID_PRO_CANLIN_PRODUCT_ID
|
||||
|
||||
static inline bool kvaser_is_leaf(const struct usb_device_id *id)
|
||||
{
|
||||
|
|
@ -187,14 +189,16 @@ static const struct usb_device_id kvaser_usb_table[] = {
|
|||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_PRO_2HS_V2_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO_2HS_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO_PRO_2HS_V2_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_CANLIN_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_2CANLIN_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_ATI_USBCAN_PRO_2HS_V2_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_ATI_MEMO_PRO_2HS_V2_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_PRO_CANLIN_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_PRO_2CANLIN_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_U100_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_U100P_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_U100S_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_PRO_4HS_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_CANLIN_PRODUCT_ID) },
|
||||
{ USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_PRO_CANLIN_PRODUCT_ID) },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(usb, kvaser_usb_table);
|
||||
|
|
|
|||
|
|
@ -123,8 +123,8 @@ struct can_frame {
|
|||
/*
|
||||
* defined bits for canfd_frame.flags
|
||||
*
|
||||
* The use of struct canfd_frame implies the Extended Data Length (EDL) bit to
|
||||
* be set in the CAN frame bitstream on the wire. The EDL bit switch turns
|
||||
* The use of struct canfd_frame implies the FD Frame (FDF) bit to
|
||||
* be set in the CAN frame bitstream on the wire. The FDF bit switch turns
|
||||
* the CAN controllers bitstream processor into the CAN FD mode which creates
|
||||
* two new options within the CAN FD frame specification:
|
||||
*
|
||||
|
|
@ -135,9 +135,18 @@ struct can_frame {
|
|||
* controller only the CANFD_BRS bit is relevant for real CAN controllers when
|
||||
* building a CAN FD frame for transmission. Setting the CANFD_ESI bit can make
|
||||
* sense for virtual CAN interfaces to test applications with echoed frames.
|
||||
*
|
||||
* The struct can_frame and struct canfd_frame intentionally share the same
|
||||
* layout to be able to write CAN frame content into a CAN FD frame structure.
|
||||
* When this is done the former differentiation via CAN_MTU / CANFD_MTU gets
|
||||
* lost. CANFD_FDF allows programmers to mark CAN FD frames in the case of
|
||||
* using struct canfd_frame for mixed CAN / CAN FD content (dual use).
|
||||
* N.B. the Kernel APIs do NOT provide mixed CAN / CAN FD content inside of
|
||||
* struct canfd_frame therefore the CANFD_FDF flag is disregarded by Linux.
|
||||
*/
|
||||
#define CANFD_BRS 0x01 /* bit rate switch (second bitrate for payload data) */
|
||||
#define CANFD_ESI 0x02 /* error state indicator of the transmitting node */
|
||||
#define CANFD_FDF 0x04 /* mark CAN FD for dual use of struct canfd_frame */
|
||||
|
||||
/**
|
||||
* struct canfd_frame - CAN flexible data rate frame structure
|
||||
|
|
|
|||
|
|
@ -221,8 +221,8 @@ static int isotp_send_fc(struct sock *sk, int ae, u8 flowstatus)
|
|||
|
||||
can_send_ret = can_send(nskb, 1);
|
||||
if (can_send_ret)
|
||||
pr_notice_once("can-isotp: %s: can_send_ret %d\n",
|
||||
__func__, can_send_ret);
|
||||
pr_notice_once("can-isotp: %s: can_send_ret %pe\n",
|
||||
__func__, ERR_PTR(can_send_ret));
|
||||
|
||||
dev_put(dev);
|
||||
|
||||
|
|
@ -797,10 +797,12 @@ isotp_tx_burst:
|
|||
can_skb_set_owner(skb, sk);
|
||||
|
||||
can_send_ret = can_send(skb, 1);
|
||||
if (can_send_ret)
|
||||
pr_notice_once("can-isotp: %s: can_send_ret %d\n",
|
||||
__func__, can_send_ret);
|
||||
|
||||
if (can_send_ret) {
|
||||
pr_notice_once("can-isotp: %s: can_send_ret %pe\n",
|
||||
__func__, ERR_PTR(can_send_ret));
|
||||
if (can_send_ret == -ENOBUFS)
|
||||
pr_notice_once("can-isotp: tx queue is full, increasing txqueuelen may prevent this error\n");
|
||||
}
|
||||
if (so->tx.idx >= so->tx.len) {
|
||||
/* we are done */
|
||||
so->tx.state = ISOTP_IDLE;
|
||||
|
|
@ -946,8 +948,8 @@ static int isotp_sendmsg(struct socket *sock, struct msghdr *msg, size_t size)
|
|||
err = can_send(skb, 1);
|
||||
dev_put(dev);
|
||||
if (err) {
|
||||
pr_notice_once("can-isotp: %s: can_send_ret %d\n",
|
||||
__func__, err);
|
||||
pr_notice_once("can-isotp: %s: can_send_ret %pe\n",
|
||||
__func__, ERR_PTR(err));
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
@ -1450,7 +1452,7 @@ static __init int isotp_module_init(void)
|
|||
|
||||
err = can_proto_register(&isotp_can_proto);
|
||||
if (err < 0)
|
||||
pr_err("can: registration of isotp protocol failed\n");
|
||||
pr_err("can: registration of isotp protocol failed %pe\n", ERR_PTR(err));
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -99,8 +99,6 @@ static void can_init_stats(struct net *net)
|
|||
static unsigned long calc_rate(unsigned long oldjif, unsigned long newjif,
|
||||
unsigned long count)
|
||||
{
|
||||
unsigned long rate;
|
||||
|
||||
if (oldjif == newjif)
|
||||
return 0;
|
||||
|
||||
|
|
@ -111,9 +109,7 @@ static unsigned long calc_rate(unsigned long oldjif, unsigned long newjif,
|
|||
return 99999999;
|
||||
}
|
||||
|
||||
rate = (count * HZ) / (newjif - oldjif);
|
||||
|
||||
return rate;
|
||||
return (count * HZ) / (newjif - oldjif);
|
||||
}
|
||||
|
||||
void can_stat_update(struct timer_list *t)
|
||||
|
|
|
|||
Loading…
Reference in a new issue