imx: add support for i.MX95 ELE/V2X MU
misc: I will be signing-off from my personal gmail id from now on. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE6EwehDt/SOnwFyTyf9lkf8eYP5UFAmXuS8UACgkQf9lkf8eY P5Ut9xAAiK6ZL5sbemKzW+SqqovFR2H2tsajORl1ySU/rFE9e3+oVMX3SEPp4vJx trd05wdrxJdBrmkmM64uKd/tMow7KUZ+fjnsDvhDiRhVvY3E+h6FiDCuHW8I6mMr SvEXF1wXA6iZQnPRg6QyJwniWJ/Ds3EA4IhkWrvqbaEB8N7djyKBKYkthL4Bg7/H l1I9e9mBw3yTwlrVjUXQjocNTqAiEHS5gJuNXH7C8Ovj7g37CpaC934uIc1M72Ww IQUMSR4QBaDYEZ1NuKrevT1Tr9FbqPMpH1BN46H0OYL4APO+gyXV1dsBPtqvItVs 2Ew5JWryQ5m1WL11pER5dUnhMz9mRfSBttrLg5JnqJO22Aif/jYgnu7hcfD1H20y 9j87hL5RH1CnuZTGg/MzakOGiv5d91U73kofVMxsYO+NbAL7qtdV/QPV1p0bd1wA 9B06gsfIfByV+v3A2qGVfle+OjW/bzRZeWpa2UqQBnw0NlsWo8EvBuU6+6Bh18IO 6zViMADGqk3uq7nzJameuABfTH8+xEWuXBJtbsZr9v3ZUZzg6M3IODSn8YdwJBWS D1FvoRBgUzSlRjEIRwGSE7GGaa/tEhI69ccqpjKQjvTYwpGFvKrg2ocEDRKLTa4L nlgDKpYoJHm7cItsG/9chxdxWiiPWmeVjx/o75qpNHTPqMglv2E= =+39i -----END PGP SIGNATURE----- Merge tag 'mailbox-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox Pull mailbox updates from Jassi Brar: - imx: add support for i.MX95 ELE/V2X MU - misc: I will be signing-off from my personal gmail id from now on * tag 'mailbox-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: mailbox: imx: support i.MX95 Generic/ELE/V2X MU mailbox: imx: populate sub-nodes mailbox: imx: get RR/TR registers num from Parameter register mailbox: imx: support return value of init dt-bindings: mailbox: fsl,mu: add i.MX95 Generic/ELE/V2X MU compatible
This commit is contained in:
Linus Torvalds
commit
9687d4ac58
2 changed files with 123 additions and 23 deletions
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@ -29,8 +29,11 @@ properties:
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- const: fsl,imx8ulp-mu
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- const: fsl,imx8-mu-scu
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- const: fsl,imx8-mu-seco
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- const: fsl,imx93-mu-s4
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- const: fsl,imx8ulp-mu-s4
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- const: fsl,imx93-mu-s4
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- const: fsl,imx95-mu
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- const: fsl,imx95-mu-ele
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- const: fsl,imx95-mu-v2x
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- items:
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- const: fsl,imx93-mu
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- const: fsl,imx8ulp-mu
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@ -95,6 +98,19 @@ properties:
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power-domains:
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maxItems: 1
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ranges: true
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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patternProperties:
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"^sram@[a-f0-9]+":
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$ref: /schemas/sram/sram.yaml#
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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@ -122,6 +138,15 @@ allOf:
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required:
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- interrupt-names
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- if:
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not:
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properties:
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compatible:
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const: fsl,imx95-mu
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then:
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patternProperties:
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"^sram@[a-f0-9]+": false
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additionalProperties: false
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examples:
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@ -134,3 +159,34 @@ examples:
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mailbox@445b0000 {
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compatible = "fsl,imx95-mu";
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reg = <0x445b0000 0x10000>;
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ranges;
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <1>;
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#mbox-cells = <2>;
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sram@445b1000 {
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compatible = "mmio-sram";
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reg = <0x445b1000 0x400>;
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ranges = <0x0 0x445b1000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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scmi-sram-section@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x80>;
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};
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scmi-sram-section@80 {
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compatible = "arm,scmi-shmem";
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reg = <0x80 0x80>;
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};
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};
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};
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@ -4,6 +4,7 @@
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* Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/firmware/imx/ipc.h>
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#include <linux/firmware/imx/s4.h>
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@ -15,6 +16,7 @@
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/suspend.h>
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@ -29,7 +31,9 @@
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#define IMX_MU_S4_CHANS 2
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#define IMX_MU_CHAN_NAME_SIZE 20
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#define IMX_MU_NUM_RR 4
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#define IMX_MU_V2_PAR_OFF 0x4
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#define IMX_MU_V2_TR_MASK GENMASK(7, 0)
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#define IMX_MU_V2_RR_MASK GENMASK(15, 8)
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#define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
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#define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
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@ -93,10 +97,11 @@ struct imx_mu_priv {
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struct clk *clk;
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int irq[IMX_MU_CHANS];
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bool suspend;
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u32 xcr[IMX_MU_xCR_MAX];
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bool side_b;
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u32 xcr[IMX_MU_xCR_MAX];
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u32 num_tr;
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u32 num_rr;
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};
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enum imx_mu_type {
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@ -110,7 +115,7 @@ struct imx_mu_dcfg {
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int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
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int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
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int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
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void (*init)(struct imx_mu_priv *priv);
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int (*init)(struct imx_mu_priv *priv);
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enum imx_mu_type type;
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u32 xTR; /* Transmit Register0 */
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u32 xRR; /* Receive Register0 */
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@ -264,18 +269,17 @@ static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
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static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
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{
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u32 *arg = data;
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u32 num_tr = priv->num_tr;
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int i, ret;
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u32 xsr;
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u32 size, max_size, num_tr;
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u32 size, max_size;
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if (priv->dcfg->type & IMX_MU_V2_S4) {
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size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
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max_size = sizeof(struct imx_s4_rpc_msg_max);
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num_tr = 8;
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} else {
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size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
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max_size = sizeof(struct imx_sc_rpc_msg_max);
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num_tr = 4;
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}
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switch (cp->type) {
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@ -324,6 +328,7 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
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int i, ret;
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u32 xsr;
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u32 size, max_size;
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u32 num_rr = priv->num_rr;
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data = (u32 *)priv->msg;
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@ -345,13 +350,13 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
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for (i = 1; i < size; i++) {
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ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
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xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,
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xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0,
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5 * USEC_PER_SEC);
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if (ret) {
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dev_err(priv->dev, "timeout read idx %d\n", i);
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return ret;
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}
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*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
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*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4);
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}
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
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@ -737,11 +742,30 @@ static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
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return imx_mu_xlate(mbox, sp);
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}
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static void imx_mu_init_generic(struct imx_mu_priv *priv)
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static void imx_mu_get_tr_rr(struct imx_mu_priv *priv)
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{
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u32 val;
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if (priv->dcfg->type & IMX_MU_V2) {
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val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF);
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priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
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priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val);
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} else {
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priv->num_tr = 4;
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priv->num_rr = 4;
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}
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}
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static int imx_mu_init_generic(struct imx_mu_priv *priv)
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{
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unsigned int i;
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unsigned int val;
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if (priv->num_rr > 4 || priv->num_tr > 4) {
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WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__);
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return -EOPNOTSUPP;
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}
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for (i = 0; i < IMX_MU_CHANS; i++) {
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struct imx_mu_con_priv *cp = &priv->con_priv[i];
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@ -757,7 +781,7 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
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priv->mbox.of_xlate = imx_mu_xlate;
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if (priv->side_b)
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return;
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return 0;
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/* Set default MU configuration */
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for (i = 0; i < IMX_MU_xCR_MAX; i++)
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@ -768,11 +792,13 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
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imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
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/* Clear any pending RSR */
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for (i = 0; i < IMX_MU_NUM_RR; i++)
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imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
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for (i = 0; i < priv->num_rr; i++)
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imx_mu_read(priv, priv->dcfg->xRR + i * 4);
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return 0;
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}
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static void imx_mu_init_specific(struct imx_mu_priv *priv)
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static int imx_mu_init_specific(struct imx_mu_priv *priv)
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{
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unsigned int i;
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int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
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@ -794,12 +820,20 @@ static void imx_mu_init_specific(struct imx_mu_priv *priv)
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/* Set default MU configuration */
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for (i = 0; i < IMX_MU_xCR_MAX; i++)
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imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
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return 0;
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}
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static void imx_mu_init_seco(struct imx_mu_priv *priv)
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static int imx_mu_init_seco(struct imx_mu_priv *priv)
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{
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imx_mu_init_generic(priv);
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int ret;
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ret = imx_mu_init_generic(priv);
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if (ret)
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return ret;
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priv->mbox.of_xlate = imx_mu_seco_xlate;
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return 0;
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}
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static int imx_mu_probe(struct platform_device *pdev)
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@ -864,9 +898,15 @@ static int imx_mu_probe(struct platform_device *pdev)
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return ret;
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}
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imx_mu_get_tr_rr(priv);
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priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
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priv->dcfg->init(priv);
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ret = priv->dcfg->init(priv);
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if (ret) {
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dev_err(dev, "Failed to init MU\n");
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goto disable_clk;
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}
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spin_lock_init(&priv->xcr_lock);
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@ -878,10 +918,10 @@ static int imx_mu_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, priv);
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ret = devm_mbox_controller_register(dev, &priv->mbox);
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if (ret) {
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clk_disable_unprepare(priv->clk);
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return ret;
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}
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if (ret)
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goto disable_clk;
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of_platform_populate(dev->of_node, NULL, NULL, dev);
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pm_runtime_enable(dev);
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@ -899,6 +939,7 @@ static int imx_mu_probe(struct platform_device *pdev)
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disable_runtime_pm:
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pm_runtime_disable(dev);
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disable_clk:
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clk_disable_unprepare(priv->clk);
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return ret;
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}
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@ -994,6 +1035,9 @@ static const struct of_device_id imx_mu_dt_ids[] = {
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{ .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
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{ .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
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{ .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
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{ .compatible = "fsl,imx95-mu", .data = &imx_mu_cfg_imx8ulp },
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{ .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 },
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{ .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 },
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{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
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{ .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
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{ },
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