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MIPS: Loongson64: Set timer mode in cpu-probe

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commit 1cb6ab4464 upstream.

Loongson64 C and G processors have EXTIMER feature which
is conflicting with CP0 counter.

Although the processor resets in EXTIMER disabled & INTIMER
enabled mode, which is compatible with MIPS CP0 compare, firmware
may attempt to enable EXTIMER and interfere CP0 compare.

Set timer mode back to MIPS compatible mode to fix booting on
systems with such firmware before we have an actual driver for
EXTIMER.

Cc: stable@vger.kernel.org
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jiaxun Yang 2024-07-23 17:15:44 +08:00 committed by Greg Kroah-Hartman
parent 6c323c3b80
commit 8cbcb6d03d
1 changed files with 4 additions and 0 deletions
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4
arch/mips/kernel/cpu-probe.c
View file

@ -1724,12 +1724,16 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER,
LOONGSON_CONF6_INTIMER);
break; break;
case PRID_IMP_LOONGSON_64G: case PRID_IMP_LOONGSON_64G:
__cpu_name[cpu] = "ICT Loongson-3"; __cpu_name[cpu] = "ICT Loongson-3";
set_elf_platform(cpu, "loongson3a"); set_elf_platform(cpu, "loongson3a");
set_isa(c, MIPS_CPU_ISA_M64R2); set_isa(c, MIPS_CPU_ISA_M64R2);
decode_cpucfg(c); decode_cpucfg(c);
change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER,
LOONGSON_CONF6_INTIMER);
break; break;
default: default:
panic("Unknown Loongson Processor ID!"); panic("Unknown Loongson Processor ID!");