- Add a x86 hw vulnerabilities section to MAINTAINERS so that the folks
involved in it can get CCed on patches - Add some more CPUID leafs to the kcpuid tool and extend its functionality to be more useful when grepping for CPUID bits -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmRGiuYACgkQEsHwGGHe VUoC2BAAsbtki6d4bds6uezRapz9RoOJUGHm4eY4drMCXe2Mz0myD8/jDV6kRKVb WWDlVEv9fxoTOHTCO7kazjrwm6wXt/MgZ51gyZx9/WyqlS27U1SCH9REHKKhzgCK OduHi741mfAXOZ1h0M3atpJvgaKzqqugVYX7whaGwVbPKAFT+DLu+lendzAe5sxv 1WG1JIhfLf0Wn4aUX9E5N9wenyGOUWHgPbE/UBSKaxO6ySi+ut4Mn2fTKZ70Lyp1 HoZMNns2RDknXD3dMcZG3ztPaLwsNoEgRkIjLolVFMnaK2L9DrVqP+6/7mCGc5er GHdFeDdtnHih9CNm4WOQtrbynrdEAM93A3u531JCpySmVSTG1j+pCTd0P020mscl It+jnVm1f0csY7/y7tUMnzzNsQRQQszTCfpiuXTZy5Ml7z68sLcDqJQfPwFZh6fX OqmplDxE127VvZESakDyFbhV600PF1aC6xRoM2pkjqKcL6uZ7JDh+s4KisMRGGGK i39PaCH+E0aJ0mIp9EvWKI7LXYot3DPUX1A+O4zjNnsnC4dNTLu34Hb8fdBxOUB0 egqcPVDIY23ELwtzF2+f7rMZ3DufEAQ2O3YP/aVRo8didepYPJpbWb/JKvpnaYXR 4Zp0gqUtKmJ6xvO0o3pECsm/Y5WmCYHKeo9CuggT6T8iTbEEedo= =hSYX -----END PGP SIGNATURE----- Merge tag 'x86_misc_for_v6.4_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull misc x86 updates from Borislav Petkov: - Add a x86 hw vulnerabilities section to MAINTAINERS so that the folks involved in it can get CCed on patches - Add some more CPUID leafs to the kcpuid tool and extend its functionality to be more useful when grepping for CPUID bits * tag 'x86_misc_for_v6.4_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: MAINTAINERS: Add x86 hardware vulnerabilities section tools/x86/kcpuid: Dump the CPUID function in detailed view tools/x86/kcpuid: Update AMD leaf Fn80000001 tools/x86/kcpuid: Fix avx512bw and avx512lvl fields in Fn00000007
This commit is contained in:
Linus Torvalds
commit
4a4a28fca6
3 changed files with 94 additions and 14 deletions
11
MAINTAINERS
11
MAINTAINERS
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@ -22663,6 +22663,17 @@ S: Maintained
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/asm
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F: arch/x86/entry/
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X86 HARDWARE VULNERABILITIES
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M: Thomas Gleixner <tglx@linutronix.de>
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M: Borislav Petkov <bp@alien8.de>
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M: Peter Zijlstra <peterz@infradead.org>
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M: Josh Poimboeuf <jpoimboe@kernel.org>
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R: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
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S: Maintained
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F: Documentation/admin-guide/hw-vuln/
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F: arch/x86/include/asm/nospec-branch.h
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F: arch/x86/kernel/cpu/bugs.c
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X86 MCE INFRASTRUCTURE
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M: Tony Luck <tony.luck@intel.com>
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M: Borislav Petkov <bp@alien8.de>
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@ -184,8 +184,8 @@
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7, 0, EBX, 27, avx512er, AVX512 Exponent Reciproca instr
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7, 0, EBX, 28, avx512cd, AVX512 Conflict Detection instr
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7, 0, EBX, 29, sha, Intel Secure Hash Algorithm Extensions instr
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7, 0, EBX, 26, avx512bw, AVX512 Byte & Word instr
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7, 0, EBX, 28, avx512vl, AVX512 Vector Length Extentions (VL)
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7, 0, EBX, 30, avx512bw, AVX512 Byte & Word instr
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7, 0, EBX, 31, avx512vl, AVX512 Vector Length Extentions (VL)
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7, 0, ECX, 0, prefetchwt1, X
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7, 0, ECX, 1, avx512vbmi, AVX512 Vector Byte Manipulation Instructions
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7, 0, ECX, 2, umip, User-mode Instruction Prevention
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@ -340,19 +340,70 @@
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# According to SDM
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# 40000000H - 4FFFFFFFH is invalid range
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# Leaf 80000001H
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# Extended Processor Signature and Feature Bits
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0x80000001, 0, ECX, 0, lahf_lm, LAHF/SAHF available in 64-bit mode
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0x80000001, 0, ECX, 5, lzcnt, LZCNT
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0x80000001, 0, ECX, 8, prefetchw, PREFETCHW
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0x80000001, 0, EAX, 27:20, extfamily, Extended family
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0x80000001, 0, EAX, 19:16, extmodel, Extended model
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0x80000001, 0, EAX, 11:8, basefamily, Description of Family
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0x80000001, 0, EAX, 11:8, basemodel, Model numbers vary with product
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0x80000001, 0, EAX, 3:0, stepping, Processor stepping (revision) for a specific model
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0x80000001, 0, EBX, 31:28, pkgtype, Specifies the package type
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0x80000001, 0, ECX, 0, lahf_lm, LAHF/SAHF available in 64-bit mode
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0x80000001, 0, ECX, 1, cmplegacy, Core multi-processing legacy mode
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0x80000001, 0, ECX, 2, svm, Indicates support for: VMRUN, VMLOAD, VMSAVE, CLGI, VMMCALL, and INVLPGA
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0x80000001, 0, ECX, 3, extapicspace, Extended APIC register space
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0x80000001, 0, ECX, 4, altmovecr8, Indicates support for LOCK MOV CR0 means MOV CR8
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0x80000001, 0, ECX, 5, lzcnt, LZCNT
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0x80000001, 0, ECX, 6, sse4a, EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support
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0x80000001, 0, ECX, 7, misalignsse, Misaligned SSE Mode
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0x80000001, 0, ECX, 8, prefetchw, PREFETCHW
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0x80000001, 0, ECX, 9, osvw, OS Visible Work-around support
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0x80000001, 0, ECX, 10, ibs, Instruction Based Sampling
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0x80000001, 0, ECX, 11, xop, Extended operation support
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0x80000001, 0, ECX, 12, skinit, SKINIT and STGI support
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0x80000001, 0, ECX, 13, wdt, Watchdog timer support
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0x80000001, 0, ECX, 15, lwp, Lightweight profiling support
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0x80000001, 0, ECX, 16, fma4, Four-operand FMA instruction support
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0x80000001, 0, ECX, 17, tce, Translation cache extension
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0x80000001, 0, ECX, 22, TopologyExtensions, Indicates support for Core::X86::Cpuid::CachePropEax0 and Core::X86::Cpuid::ExtApicId
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0x80000001, 0, ECX, 23, perfctrextcore, Indicates support for Core::X86::Msr::PERF_CTL0 - 5 and Core::X86::Msr::PERF_CTR
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0x80000001, 0, ECX, 24, perfctrextdf, Indicates support for Core::X86::Msr::DF_PERF_CTL and Core::X86::Msr::DF_PERF_CTR
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0x80000001, 0, ECX, 26, databreakpointextension, Indicates data breakpoint support for Core::X86::Msr::DR0_ADDR_MASK, Core::X86::Msr::DR1_ADDR_MASK, Core::X86::Msr::DR2_ADDR_MASK and Core::X86::Msr::DR3_ADDR_MASK
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0x80000001, 0, ECX, 27, perftsc, Performance time-stamp counter supported
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0x80000001, 0, ECX, 28, perfctrextllc, Indicates support for L3 performance counter extensions
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0x80000001, 0, ECX, 29, mwaitextended, MWAITX and MONITORX capability is supported
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0x80000001, 0, ECX, 30, admskextn, Indicates support for address mask extension (to 32 bits and to all 4 DRs) for instruction breakpoints
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0x80000001, 0, EDX, 0, fpu, x87 floating point unit on-chip
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0x80000001, 0, EDX, 1, vme, Virtual-mode enhancements
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0x80000001, 0, EDX, 2, de, Debugging extensions, IO breakpoints, CR4.DE
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0x80000001, 0, EDX, 3, pse, Page-size extensions (4 MB pages)
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0x80000001, 0, EDX, 4, tsc, Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD
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0x80000001, 0, EDX, 5, msr, Model-specific registers (MSRs), with RDMSR and WRMSR instructions
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0x80000001, 0, EDX, 6, pae, Physical-address extensions (PAE)
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0x80000001, 0, EDX, 7, mce, Machine Check Exception, CR4.MCE
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0x80000001, 0, EDX, 8, cmpxchg8b, CMPXCHG8B instruction
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0x80000001, 0, EDX, 9, apic, advanced programmable interrupt controller (APIC) exists and is enabled
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0x80000001, 0, EDX, 11, sysret, SYSCALL/SYSRET supported
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0x80000001, 0, EDX, 12, mtrr, Memory-type range registers
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0x80000001, 0, EDX, 13, pge, Page global extension, CR4.PGE
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0x80000001, 0, EDX, 14, mca, Machine check architecture, MCG_CAP
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0x80000001, 0, EDX, 15, cmov, Conditional move instructions, CMOV, FCOMI, FCMOV
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0x80000001, 0, EDX, 16, pat, Page attribute table
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0x80000001, 0, EDX, 17, pse36, Page-size extensions
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0x80000001, 0, EDX, 20, exec_dis, Execute Disable Bit available
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0x80000001, 0, EDX, 22, mmxext, AMD extensions to MMX instructions
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0x80000001, 0, EDX, 23, mmx, MMX instructions
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0x80000001, 0, EDX, 24, fxsr, FXSAVE and FXRSTOR instructions
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0x80000001, 0, EDX, 25, ffxsr, FXSAVE and FXRSTOR instruction optimizations
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0x80000001, 0, EDX, 26, 1gb_page, 1GB page supported
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0x80000001, 0, EDX, 27, rdtscp, RDTSCP and IA32_TSC_AUX are available
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#0x80000001, 0, EDX, 29, 64b, 64b Architecture supported
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0x80000001, 0, EDX, 29, lm, 64b Architecture supported
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0x80000001, 0, EDX, 30, threednowext, AMD extensions to 3DNow! instructions
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0x80000001, 0, EDX, 31, threednow, 3DNow! instructions
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# Leaf 80000002H/80000003H/80000004H
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# Processor Brand String
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Can't render this file because it has a wrong number of fields in line 110.
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@ -33,7 +33,7 @@ struct reg_desc {
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struct bits_desc descs[32];
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};
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enum {
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enum cpuid_reg {
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R_EAX = 0,
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R_EBX,
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R_ECX,
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@ -41,6 +41,10 @@ enum {
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NR_REGS
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};
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static const char * const reg_names[] = {
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"EAX", "EBX", "ECX", "EDX",
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};
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struct subleaf {
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u32 index;
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u32 sub;
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@ -428,12 +432,18 @@ static void parse_text(void)
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/* Decode every eax/ebx/ecx/edx */
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static void decode_bits(u32 value, struct reg_desc *rdesc)
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static void decode_bits(u32 value, struct reg_desc *rdesc, enum cpuid_reg reg)
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{
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struct bits_desc *bdesc;
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int start, end, i;
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u32 mask;
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if (!rdesc->nr) {
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if (show_details)
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printf("\t %s: 0x%08x\n", reg_names[reg], value);
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return;
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}
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for (i = 0; i < rdesc->nr; i++) {
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bdesc = &rdesc->descs[i];
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@ -468,13 +478,21 @@ static void show_leaf(struct subleaf *leaf)
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if (!leaf)
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return;
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if (show_raw)
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if (show_raw) {
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leaf_print_raw(leaf);
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} else {
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if (show_details)
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printf("CPUID_0x%x_ECX[0x%x]:\n",
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leaf->index, leaf->sub);
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}
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decode_bits(leaf->eax, &leaf->info[R_EAX]);
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decode_bits(leaf->ebx, &leaf->info[R_EBX]);
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decode_bits(leaf->ecx, &leaf->info[R_ECX]);
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decode_bits(leaf->edx, &leaf->info[R_EDX]);
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decode_bits(leaf->eax, &leaf->info[R_EAX], R_EAX);
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decode_bits(leaf->ebx, &leaf->info[R_EBX], R_EBX);
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decode_bits(leaf->ecx, &leaf->info[R_ECX], R_ECX);
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decode_bits(leaf->edx, &leaf->info[R_EDX], R_EDX);
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if (!show_raw && show_details)
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printf("\n");
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}
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static void show_func(struct cpuid_func *func)
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