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ARM: SoC drivers for 6.6

Browse source 
The main change this time is the introduction of the drivers/genpd
 subsystem that gets split out from drivers/soc to keep common
 functionality together. Ulf Hansson is taking over maintainership for
 these and is sending a separate pull request with the same commits,
 but they are in the soc drivers tree to avoid conflicts against other
 soc driver patches.
 
 The SCMI driver subsystem gets an update to version 3.2 of the
 specification. There are also updates to memory, reset and other firmware
 drivers.
 
 On the soc driver side, the updates are mostly cleanups across a number
 of Arm platforms. On driver for loongarch adds power management for DT
 based systems, another driver is for HiSilicon's Arm server chips with
 their HCCS system health interface.
 
 The remaining updates for the most part add support for additional
 hardware in existing drivers or contain minor cleanups. Most of these
 are for the Qualcomm Snapdragon platform.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTuWdMACgkQYKtH/8kJ
 UicprBAAsvZ5h636MOwYasgK1bKnsWgj9yrBSzIf7VzKbBS5/QCrDSDek9oDvTBp
 p6Rr+WC1RQl9i2DiRVSbEqkUS6X4hQF0kJdLudBwYuxBDf8ayzFzKAKk/ecsyoaC
 0Rkeh4fCu1zVnQ2DZSPFJVRl01/oCr1ZtJ1W0UrXCslOSQy2987VqpJ/EQbaDLgb
 3imxpvJNBscaKwcYRgxhcIMBLdGi3qXRE/TmAf1WMe8w6dfk5KmFiPPD7zxPTnFb
 0fssdxgocjOkXEn6L1VdBMoTt4UQaU+xbnFsOsDA/F0EjR9ZLlhtwZxANv4GicP6
 52FMFaxeXSUnpBelzuyRQpgnt9WW3ZbBGb9iaisTl1pwjC3PcN2noo8uFZk+kO6b
 8q0fh4KVmD0QIupC4cfTsF4SGAQvnhko2ls9bt4FTF+z0COV3Ifs2cAggH+hn3yD
 IziBrUUZrR4G8XhisJRQNZcRh1H/vVchcumqsxzCMhpXLWwdZ5vW85GCR/fAtQQT
 woYgqFHXZjEko66bu2dtayr1dgmPvfbO6rXpUkIdeskY6XuKfZXuB93LkhsZ17LY
 dfAaBLUebjMcpLrltCqyP1tUoqGyVOTJKxtB2MolHo/V/2JbKYmYHAMy+qX5I0Qm
 UUbQDpHnkaQMTK2L/qvdfE4lgwWfFWX7lCK/AGa4ZBFl+Zl6DgE=
 =xmHW
 -----END PGP SIGNATURE-----

Merge tag 'soc-drivers-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "The main change this time was the introduction of the drivers/genpd
  subsystem that gets split out from drivers/soc to keep common
  functionality together.

  The SCMI driver subsystem gets an update to version 3.2 of the
  specification. There are also updates to memory, reset and other
  firmware drivers.

  On the soc driver side, the updates are mostly cleanups across a
  number of Arm platforms. On driver for loongarch adds power management
  for DT based systems, another driver is for HiSilicon's Arm server
  chips with their HCCS system health interface.

  The remaining updates for the most part add support for additional
  hardware in existing drivers or contain minor cleanups. Most of these
  are for the Qualcomm Snapdragon platform"

* tag 'soc-drivers-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (136 commits)
  bus: fsl-mc: Use common ranges functions
  soc: kunpeng_hccs: fix some sparse warnings about incorrect type
  soc: loongson2_pm: add power management support
  soc: dt-bindings: add loongson-2 pm
  soc: rockchip: grf: Fix SDMMC not working on RK3588 with bus-width > 1
  genpd: rockchip: Add PD_VO entry for rv1126
  bus: ti-sysc: Fix cast to enum warning
  soc: kunpeng_hccs: add MAILBOX dependency
  MAINTAINERS: remove OXNAS entry
  dt-bindings: interrupt-controller: arm,versatile-fpga-irq: mark oxnas compatible as deprecated
  irqchip: irq-versatile-fpga: remove obsolete oxnas compatible
  soc: qcom: aoss: Tidy up qmp_send() callers
  soc: qcom: aoss: Format string in qmp_send()
  soc: qcom: aoss: Move length requirements from caller
  soc: kunpeng_hccs: fix size_t format string
  soc: ti: k3-socinfo.c: Add JTAG ID for AM62PX
  dt-bindings: firmware: qcom: scm: Updating VMID list
  firmware: imx: scu-irq: support identifying SCU wakeup source from sysfs
  firmware: imx: scu-irq: enlarge the IMX_SC_IRQ_NUM_GROUP
  firmware: imx: scu-irq: add imx_scu_irq_get_status
  ...
This commit is contained in:
Linus Torvalds 2023-08-30 16:42:21 -07:00
commit 1544df9ab4
166 changed files with 3827 additions and 1113 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

81
Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs Normal file
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@ -0,0 +1,81 @@
What: /sys/devices/platform/HISI04Bx:00/chipX/all_linked
What: /sys/devices/platform/HISI04Bx:00/chipX/linked_full_lane
What: /sys/devices/platform/HISI04Bx:00/chipX/crc_err_cnt
Date: November 2023
KernelVersion: 6.6
Contact: Huisong Li <lihuisong@huawei.org>
Description:
The /sys/devices/platform/HISI04Bx:00/chipX/ directory
contains read-only attributes exposing some summarization
information of all HCCS ports under a specified chip.
The X in 'chipX' indicates the Xth chip on platform.
There are following attributes in this directory:
================= ==== =========================================
all_linked: (RO) if all enabled ports on this chip are
linked (bool).
linked_full_lane: (RO) if all linked ports on this chip are full
lane (bool).
crc_err_cnt: (RO) total CRC err count for all ports on this
chip.
================= ==== =========================================
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/all_linked
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/linked_full_lane
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/crc_err_cnt
Date: November 2023
KernelVersion: 6.6
Contact: Huisong Li <lihuisong@huawei.org>
Description:
The /sys/devices/platform/HISI04Bx:00/chipX/dieY/ directory
contains read-only attributes exposing some summarization
information of all HCCS ports under a specified die.
The Y in 'dieY' indicates the hardware id of the die on chip who
has chip id X.
There are following attributes in this directory:
================= ==== =========================================
all_linked: (RO) if all enabled ports on this die are
linked (bool).
linked_full_lane: (RO) if all linked ports on this die are full
lane (bool).
crc_err_cnt: (RO) total CRC err count for all ports on this
die.
================= ==== =========================================
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/type
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mode
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/enable
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/cur_lane_num
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/link_fsm
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mask
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/crc_err_cnt
Date: November 2023
KernelVersion: 6.6
Contact: Huisong Li <lihuisong@huawei.org>
Description:
The /sys/devices/platform/HISI04Bx/chipX/dieX/hccsN/ directory
contains read-only attributes exposing information about
a HCCS port. The N value in 'hccsN' indicates this port id.
The X in 'chipX' indicates the ID of the chip to which the
HCCS port belongs. For example, X ranges from to 'n - 1' if the
chip number on platform is n.
The Y in 'dieY' indicates the hardware id of the die to which
the hccs port belongs.
Note: type, lane_mode and enable are fixed attributes on running
platform.
The HCCS port have the following attributes:
============= ==== =============================================
type: (RO) port type (string), e.g. HCCS-v1 -> H32
lane_mode: (RO) the lane mode of this port (string), e.g. x8
enable: (RO) indicate if this port is enabled (bool).
cur_lane_num: (RO) current lane number of this port.
link_fsm: (RO) link finite state machine of this port.
lane_mask: (RO) current lane mask of this port, every bit
indicates a lane.
crc_err_cnt: (RO) CRC err count on this port.
============= ==== =============================================

4
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
View file

@ -82,7 +82,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8250-dispcc";
reg = <0x0af00000 0x10000>;
@ -103,7 +103,7 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8250_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

4
Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml
View file

@ -51,7 +51,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@abf0000 {
compatible = "qcom,sm8350-videocc";
@ -59,7 +59,7 @@ examples:
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SM8350_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;

4
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View file

@ -64,7 +64,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@ade0000 {
compatible = "qcom,sm8450-camcc";
reg = <0xade0000 0x20000>;
@ -72,7 +72,7 @@ examples:
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;

4
Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
View file

@ -76,7 +76,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8450-dispcc";
reg = <0x0af00000 0x10000>;
@ -91,7 +91,7 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

4
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
View file

@ -64,13 +64,13 @@ examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
videocc: clock-controller@aaf0000 {
compatible = "qcom,sm8450-videocc";
reg = <0x0aaf0000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_VIDEO_AHB_CLK>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;

4
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
View file

@ -76,7 +76,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8550-dispcc";
reg = <0x0af00000 0x10000>;
@ -99,7 +99,7 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

4
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
View file

@ -124,7 +124,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@ab00000 {
compatible = "qcom,sdm845-videocc";
reg = <0x0ab00000 0x10000>;
@ -133,7 +133,7 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8250_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

4
Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml
View file

@ -54,7 +54,7 @@ examples:
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-controller@ae01000 {
compatible = "qcom,sm8250-dpu";
@ -72,7 +72,7 @@ examples:
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;

8
Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml
View file

@ -76,7 +76,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-subsystem@ae00000 {
compatible = "qcom,sm8250-mdss";
@ -121,7 +121,7 @@ examples:
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
@ -196,7 +196,7 @@ examples:
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&dsi0_phy>;
phy-names = "dsi";
@ -286,7 +286,7 @@ examples:
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&dsi1_phy>;
phy-names = "dsi";

4
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
View file

@ -51,7 +51,7 @@ examples:
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-controller@ae01000 {
compatible = "qcom,sm8350-dpu";
@ -76,7 +76,7 @@ examples:
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8350_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;

6
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
View file

@ -81,7 +81,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-subsystem@ae00000 {
compatible = "qcom,sm8350-mdss";
@ -134,7 +134,7 @@ examples:
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8350_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
@ -203,7 +203,7 @@ examples:
<&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SM8350_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&mdss_dsi0_phy>;

4
Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
View file

@ -58,7 +58,7 @@ examples:
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-controller@ae01000 {
compatible = "qcom,sm8450-dpu";
@ -83,7 +83,7 @@ examples:
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;

8
Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
View file

@ -76,7 +76,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-subsystem@ae00000 {
compatible = "qcom,sm8450-mdss";
@ -130,7 +130,7 @@ examples:
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
@ -210,7 +210,7 @@ examples:
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&dsi0_phy>;
phy-names = "dsi";
@ -305,7 +305,7 @@ examples:
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&dsi1_phy>;
phy-names = "dsi";

4
Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
View file

@ -57,7 +57,7 @@ examples:
#include <dt-bindings/clock/qcom,sm8550-dispcc.h>
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-controller@ae01000 {
compatible = "qcom,sm8550-dpu";
@ -82,7 +82,7 @@ examples:
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;

8
Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml
View file

@ -76,7 +76,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-subsystem@ae00000 {
compatible = "qcom,sm8550-mdss";
@ -130,7 +130,7 @@ examples:
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
@ -205,7 +205,7 @@ examples:
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&dsi0_phy>;
phy-names = "dsi";
@ -294,7 +294,7 @@ examples:
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&dsi1_phy>;
phy-names = "dsi";

1
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
View file

@ -176,6 +176,7 @@ allOf:
contains:
enum:
- qcom,scm-qdu1000
- qcom,scm-sc8280xp
- qcom,scm-sm8450
- qcom,scm-sm8550
then:

4
Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt
View file

@ -6,7 +6,7 @@ controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
instance can handle up to 32 interrupts.
Required properties:
- compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
- compatible: "arm,versatile-fpga-irq"
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: The number of cells to define the interrupts. Must be 1
as the FPGA IRQ controller has no configuration options for interrupt
@ -19,6 +19,8 @@ Required properties:
the system till not make it possible for devices to request these
interrupts.
The "oxsemi,ox810se-rps-irq" compatible is deprecated.
Example:
pic: pic@14000000 {

4
Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
View file

@ -106,7 +106,7 @@ examples:
#include <dt-bindings/clock/qcom,videocc-sm8250.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
venus: video-codec@aa00000 {
compatible = "qcom,sm8250-venus";
@ -114,7 +114,7 @@ examples:
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&videocc MVS0C_GDSC>,
<&videocc MVS0_GDSC>,
<&rpmhpd SM8250_MX>;
<&rpmhpd RPMHPD_MX>;
power-domain-names = "venus", "vcodec0", "mx";
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,

1
Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
View file

@ -39,6 +39,7 @@ properties:
patternProperties:
".*@[0-9]+$":
type: object
$ref: mc-peripheral-props.yaml#
required:
- compatible

2
Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
View file

@ -34,6 +34,8 @@ required:
# The controller specific properties go here.
allOf:
- $ref: st,stm32-fmc2-ebi-props.yaml#
- $ref: ingenic,nemc-peripherals.yaml#
- $ref: intel,ixp4xx-expansion-peripheral-props.yaml#
- $ref: ti,gpmc-child.yaml#
additionalProperties: true

4
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
View file

@ -215,7 +215,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
sdhc_2: mmc@8804000 {
compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
@ -232,7 +232,7 @@ examples:
iommus = <&apps_smmu 0x4a0 0x0>;
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&sdhc2_opp_table>;

59
Documentation/devicetree/bindings/net/davicom,dm9000.yaml Normal file
View file

@ -0,0 +1,59 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/davicom,dm9000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Davicom DM9000 Fast Ethernet Controller
maintainers:
- Paul Cercueil <paul@crapouillou.net>
properties:
compatible:
const: davicom,dm9000
reg:
items:
- description: Address registers
- description: Data registers
interrupts:
maxItems: 1
davicom,no-eeprom:
type: boolean
description: Configuration EEPROM is not available
davicom,ext-phy:
type: boolean
description: Use external PHY
reset-gpios:
maxItems: 1
vcc-supply: true
required:
- compatible
- reg
- interrupts
allOf:
- $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
- $ref: /schemas/net/ethernet-controller.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
ethernet@a8000000 {
compatible = "davicom,dm9000";
reg = <0xa8000000 0x2>, <0xa8000002 0x2>;
interrupt-parent = <&gph1>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
local-mac-address = [00 00 de ad be ef];
davicom,no-eeprom;
};

27
Documentation/devicetree/bindings/net/davicom-dm9000.txt
View file

@ -1,27 +0,0 @@
Davicom DM9000 Fast Ethernet controller
Required properties:
- compatible = "davicom,dm9000";
- reg : physical addresses and sizes of registers, must contain 2 entries:
first entry : address register,
second entry : data register.
- interrupts : interrupt specifier specific to interrupt controller
Optional properties:
- davicom,no-eeprom : Configuration EEPROM is not available
- davicom,ext-phy : Use external PHY
- reset-gpios : phandle of gpio that will be used to reset chip during probe
- vcc-supply : phandle of regulator that will be used to enable power to chip
Example:
ethernet@18000000 {
compatible = "davicom,dm9000";
reg = <0x18000000 0x2 0x18000004 0x2>;
interrupt-parent = <&gpn>;
interrupts = <7 4>;
local-mac-address = [00 00 de ad be ef];
davicom,no-eeprom;
reset-gpios = <&gpf 12 GPIO_ACTIVE_LOW>;
vcc-supply = <&eth0_power>;
};

3
Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
View file

@ -12,7 +12,7 @@ maintainers:
- Jianxin Pan <jianxin.pan@amlogic.com>
description: |+
Secure Power Domains used in Meson A1/C1/S4 SoCs, and should be the child node
Secure Power Domains used in Meson A1/C1/S4 & C3 SoCs, and should be the child node
of secure-monitor.
properties:
@ -20,6 +20,7 @@ properties:
enum:
- amlogic,meson-a1-pwrc
- amlogic,meson-s4-pwrc
- amlogic,c3-pwrc
"#power-domain-cells":
const: 1

1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
View file

@ -41,6 +41,7 @@ properties:
- qcom,sdm845-rpmhpd
- qcom,sdx55-rpmhpd
- qcom,sdx65-rpmhpd
- qcom,sdx75-rpmhpd
- qcom,sm6115-rpmpd
- qcom,sm6125-rpmpd
- qcom,sm6350-rpmhpd

3
Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml
View file

@ -14,9 +14,6 @@ description:
related to the remote processor.
properties:
$nodename:
const: glink-edge
apr:
$ref: /schemas/soc/qcom/qcom,apr.yaml#
required:

2
Documentation/devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml
View file

@ -84,7 +84,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
rpm-glink {
glink-edge {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 0>;

171
Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml Normal file
View file

@ -0,0 +1,171 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,rpm-proc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Resource Power Manager (RPM) Processor/Subsystem
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Stephan Gerhold <stephan@gerhold.net>
description: |
Resource Power Manager (RPM) subsystem found in various Qualcomm platforms:
+--------------------------------------------+
| RPM subsystem (qcom,rpm-proc) |
| |
reset | +---------------+ +-----+ +-----+ |
--------->| | | MPM | | CPR | ... |
IPC interrupts | | ARM Cortex-M3 |--- +-----+ +-----+ |
----------------->| | | | | |
| +---------------+ |---------------------- |
| +---------------+ | |
| | Code RAM |--| +------------------+ |
| +---------------+ | | | |
| +---------------+ |--| Message RAM | |
| | Data RAM |--| | | |
| +---------------+ | +------------------+ |
+--------------------|-----------------------+
v
NoC
The firmware running on the processor inside the RPM subsystem allows each
component in the system to vote for state of the system resources, such as
clocks, regulators and bus frequencies. It implements multiple separate
communication interfaces that are described in subnodes, e.g. SMD and MPM:
+------------------------------+
| ARM Cortex-M3 |
| | +------------------------------+
| +--------------------------+ | | Message RAM |
| | RPM firmware | | | |
IPC IRQ 0 | | +----------------------+ | | | +--------------------------+ |
-------------->| SMD server |<------->| SMD data structures | |
| | | +--------------+ | | | | | +--------------+ | |
| | | | rpm_requests | ... | | | | | | rpm_requests | ... | |
| | | +--------------+ | | | | | +--------------+ | |
IPC IRQ 1 | | +----------------------+ | | | +--------------------------+ |
-------------->| MPM virtualization |<--------| MPM register copy (vMPM) | |
| | +----------------------+ | | | +--------------------------+ |
| | ... | | | | ... |
| +--------------------|-----+ | +------------------------------+
+----------------------|-------+
v
+--------------+
| MPM Hardware |
+--------------+
The services provided by the firmware are only available after the firmware
has been loaded and the processor has been released from reset. Usually this
happens early in the boot process before the operating system is started.
properties:
compatible:
items:
- enum:
- qcom,apq8084-rpm-proc
- qcom,ipq6018-rpm-proc
- qcom,ipq9574-rpm-proc
- qcom,mdm9607-rpm-proc
- qcom,msm8226-rpm-proc
- qcom,msm8610-rpm-proc
- qcom,msm8909-rpm-proc
- qcom,msm8916-rpm-proc
- qcom,msm8917-rpm-proc
- qcom,msm8936-rpm-proc
- qcom,msm8937-rpm-proc
- qcom,msm8952-rpm-proc
- qcom,msm8953-rpm-proc
- qcom,msm8974-rpm-proc
- qcom,msm8976-rpm-proc
- qcom,msm8994-rpm-proc
- qcom,msm8996-rpm-proc
- qcom,msm8998-rpm-proc
- qcom,qcm2290-rpm-proc
- qcom,qcs404-rpm-proc
- qcom,sdm660-rpm-proc
- qcom,sm6115-rpm-proc
- qcom,sm6125-rpm-proc
- qcom,sm6375-rpm-proc
- const: qcom,rpm-proc
smd-edge:
$ref: /schemas/remoteproc/qcom,smd-edge.yaml#
description:
Qualcomm Shared Memory subnode which represents communication edge,
channels and devices related to the RPM subsystem.
glink-edge:
$ref: /schemas/remoteproc/qcom,glink-rpm-edge.yaml#
description:
Qualcomm G-Link subnode which represents communication edge,
channels and devices related to the RPM subsystem.
interrupt-controller:
type: object
$ref: /schemas/interrupt-controller/qcom,mpm.yaml#
description:
MSM Power Manager (MPM) interrupt controller that monitors interrupts
when the system is asleep.
master-stats:
$ref: /schemas/soc/qcom/qcom,rpm-master-stats.yaml#
description:
Subsystem-level low-power mode statistics provided by RPM.
required:
- compatible
oneOf:
- required:
- smd-edge
- required:
- glink-edge
additionalProperties: false
examples:
# SMD
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
remoteproc {
compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm-requests {
compatible = "qcom,rpm-msm8916";
qcom,smd-channels = "rpm_requests";
/* ... */
};
};
};
# GLINK
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
remoteproc {
compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc";
glink-edge {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm-requests {
compatible = "qcom,rpm-qcm2290";
qcom,glink-channels = "rpm_requests";
/* ... */
};
};
};

6
Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml
View file

@ -139,7 +139,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
remoteproc@30000000 {
compatible = "qcom,sm8450-adsp-pas";
@ -160,8 +160,8 @@ examples:
memory-region = <&adsp_mem>;
power-domains = <&rpmhpd SM8450_LCX>,
<&rpmhpd SM8450_LMX>;
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
qcom,qmp = <&aoss_qmp>;

1
Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
View file

@ -32,6 +32,7 @@ properties:
enum:
- xlnx,zynqmp-reset
- xlnx,versal-reset
- xlnx,versal-net-reset
"#reset-cells":
const: 1

52
Documentation/devicetree/bindings/soc/loongson/loongson,ls2k-pmc.yaml Normal file
View file

@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/loongson/loongson,ls2k-pmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson-2 Power Manager controller
maintainers:
- Yinbo Zhu <zhuyinbo@loongson.cn>
properties:
compatible:
items:
- enum:
- loongson,ls2k0500-pmc
- loongson,ls2k1000-pmc
- const: syscon
reg:
maxItems: 1
interrupts:
maxItems: 1
loongson,suspend-address:
$ref: /schemas/types.yaml#/definitions/uint64
description:
The "loongson,suspend-address" is a deep sleep state (Suspend To
RAM) firmware entry address which was jumped from kernel and it's
value was dependent on specific platform firmware code. In
addition, the PM need according to it to indicate that current
SoC whether support Suspend To RAM.
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
power-management@1fe27000 {
compatible = "loongson,ls2k1000-pmc", "syscon";
reg = <0x1fe27000 0x58>;
interrupt-parent = <&liointc1>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
loongson,suspend-address = <0x0 0x1c000500>;
};

23
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
View file

@ -34,22 +34,27 @@ properties:
- qcom,rpm-apq8084
- qcom,rpm-ipq6018
- qcom,rpm-ipq9574
- qcom,rpm-mdm9607
- qcom,rpm-msm8226
- qcom,rpm-msm8610
- qcom,rpm-msm8909
- qcom,rpm-msm8916
- qcom,rpm-msm8917
- qcom,rpm-msm8936
- qcom,rpm-msm8937
- qcom,rpm-msm8952
- qcom,rpm-msm8953
- qcom,rpm-msm8974
- qcom,rpm-msm8976
- qcom,rpm-msm8994
- qcom,rpm-msm8996
- qcom,rpm-msm8998
- qcom,rpm-qcm2290
- qcom,rpm-qcs404
- qcom,rpm-sdm660
- qcom,rpm-sm6115
- qcom,rpm-sm6125
- qcom,rpm-sm6375
- qcom,rpm-qcm2290
- qcom,rpm-qcs404
clock-controller:
$ref: /schemas/clock/qcom,rpmcc.yaml#
@ -81,12 +86,18 @@ if:
contains:
enum:
- qcom,rpm-apq8084
- qcom,rpm-mdm9607
- qcom,rpm-msm8226
- qcom,rpm-msm8610
- qcom,rpm-msm8909
- qcom,rpm-msm8916
- qcom,rpm-msm8917
- qcom,rpm-msm8936
- qcom,rpm-msm8937
- qcom,rpm-msm8952
- qcom,rpm-msm8953
- qcom,rpm-msm8974
- qcom,rpm-msm8976
- qcom,rpm-msm8953
- qcom,rpm-msm8994
then:
properties:
@ -109,10 +120,10 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
smd {
compatible = "qcom,smd";
remoteproc {
compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
rpm {
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;

7
Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml
View file

@ -15,6 +15,12 @@ description:
The Qualcomm Shared Memory Driver is a FIFO based communication channel for
sending data between the various subsystems in Qualcomm platforms.
Using the top-level SMD node is deprecated. Instead, the SMD edges are defined
directly below the device node representing the respective remote subsystem
or remote processor.
deprecated: true
properties:
compatible:
const: qcom,smd
@ -37,6 +43,7 @@ examples:
# The following example represents a smd node, with one edge representing the
# "rpm" subsystem. For the "rpm" subsystem we have a device tied to the
# "rpm_request" channel.
# NOTE: This is deprecated, represent the RPM using "qcom,rpm-proc" instead.
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>

26
Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
View file

@ -15,7 +15,9 @@ description: |
properties:
compatible:
const: qcom,msm8974-ocmem
enum:
- qcom,msm8226-ocmem # v1.1.0
- qcom,msm8974-ocmem # v1.4.0
reg:
items:
@ -28,11 +30,13 @@ properties:
- const: mem
clocks:
minItems: 1
items:
- description: Core clock
- description: Interface clock
clock-names:
minItems: 1
items:
- const: core
- const: iface
@ -58,6 +62,26 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8974-ocmem
then:
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
else:
properties:
clocks:
minItems: 1
clock-names:
minItems: 1
patternProperties:
"-sram@[0-9a-f]+$":
type: object

43
MAINTAINERS
View file

@ -2508,16 +2508,6 @@ S: Maintained
W: http://www.digriz.org.uk/ts78xx/kernel
F: arch/arm/mach-orion5x/ts78xx-*
ARM/OXNAS platform support
M: Neil Armstrong <neil.armstrong@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-oxnas@groups.io (moderated for non-subscribers)
S: Maintained
F: arch/arm/boot/dts/ox8*.dts*
F: arch/arm/mach-oxnas/
F: drivers/power/reset/oxnas-restart.c
N: oxnas
ARM/QUALCOMM CHROMEBOOK SUPPORT
R: cros-qcom-dts-watchers@chromium.org
F: arch/arm64/boot/dts/qcom/sc7180*
@ -2945,14 +2935,13 @@ M: Sudeep Holla <sudeep.holla@arm.com>
M: Lorenzo Pieralisi <lpieralisi@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: */*/*/vexpress*
F: */*/vexpress*
F: arch/arm/boot/dts/arm/vexpress*
N: mps2
N: vexpress
F: arch/arm/mach-versatile/
F: arch/arm64/boot/dts/arm/
F: drivers/clk/versatile/clk-vexpress-osc.c
F: drivers/clocksource/timer-versatile.c
N: mps2
X: drivers/cpufreq/vexpress-spc-cpufreq.c
X: Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
ARM/VFP SUPPORT
M: Russell King <linux@armlinux.org.uk>
@ -5402,7 +5391,7 @@ M: Kukjin Kim <kgene@kernel.org>
R: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
L: linux-pm@vger.kernel.org
L: linux-samsung-soc@vger.kernel.org
S: Supported
S: Maintained
F: arch/arm/mach-exynos/pm.c
F: drivers/cpuidle/cpuidle-exynos.c
F: include/linux/platform_data/cpuidle-exynos.h
@ -9378,6 +9367,13 @@ W: https://www.hisilicon.com
F: Documentation/devicetree/bindings/i2c/hisilicon,ascend910-i2c.yaml
F: drivers/i2c/busses/i2c-hisi.c
HISILICON KUNPENG SOC HCCS DRIVER
M: Huisong Li <lihuisong@huawei.com>
S: Maintained
F: Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs
F: drivers/soc/hisilicon/kunpeng_hccs.c
F: drivers/soc/hisilicon/kunpeng_hccs.h
HISILICON LPC BUS DRIVER
M: Jay Fang <f.fangjian@huawei.com>
S: Maintained
@ -12353,6 +12349,13 @@ S: Maintained
F: Documentation/devicetree/bindings/hwinfo/loongson,ls2k-chipid.yaml
F: drivers/soc/loongson/loongson2_guts.c
LOONGSON-2 SOC SERIES PM DRIVER
M: Yinbo Zhu <zhuyinbo@loongson.cn>
L: linux-pm@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/soc/loongson/loongson,ls2k-pmc.yaml
F: drivers/soc/loongson/loongson2_pm.c
LOONGSON-2 SOC SERIES PINCTRL DRIVER
M: zhanghongchen <zhanghongchen@loongson.cn>
M: Yinbo Zhu <zhuyinbo@loongson.cn>
@ -12902,7 +12905,7 @@ F: drivers/power/supply/max77976_charger.c
MAXIM MUIC CHARGER DRIVERS FOR EXYNOS BASED BOARDS
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
L: linux-pm@vger.kernel.org
S: Supported
S: Maintained
B: mailto:linux-samsung-soc@vger.kernel.org
F: Documentation/devicetree/bindings/power/supply/maxim,max14577.yaml
F: Documentation/devicetree/bindings/power/supply/maxim,max77693.yaml
@ -12913,7 +12916,7 @@ MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BOARDS
M: Chanwoo Choi <cw00.choi@samsung.com>
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
L: linux-kernel@vger.kernel.org
S: Supported
S: Maintained
B: mailto:linux-samsung-soc@vger.kernel.org
F: Documentation/devicetree/bindings/*/maxim,max14577.yaml
F: Documentation/devicetree/bindings/*/maxim,max77686.yaml
@ -18884,7 +18887,7 @@ SAMSUNG MULTIFUNCTION PMIC DEVICE DRIVERS
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
L: linux-kernel@vger.kernel.org
L: linux-samsung-soc@vger.kernel.org
S: Supported
S: Maintained
B: mailto:linux-samsung-soc@vger.kernel.org
F: Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml
F: Documentation/devicetree/bindings/mfd/samsung,s2m*.yaml
@ -18956,7 +18959,7 @@ M: Tomasz Figa <tomasz.figa@gmail.com>
M: Chanwoo Choi <cw00.choi@samsung.com>
R: Alim Akhtar <alim.akhtar@samsung.com>
L: linux-samsung-soc@vger.kernel.org
S: Supported
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
F: Documentation/devicetree/bindings/clock/samsung,*.yaml

3
drivers/bus/Kconfig
View file

@ -210,7 +210,8 @@ config TI_PWMSS
config TI_SYSC
bool "TI sysc interconnect target module driver"
depends on ARCH_OMAP2PLUS
depends on ARCH_OMAP2PLUS || ARCH_K3
default y
help
Generic driver for Texas Instruments interconnect target module
found on many TI SoCs.

90
drivers/bus/fsl-mc/fsl-mc-bus.c
View file

@ -994,75 +994,18 @@ struct fsl_mc_device *fsl_mc_get_endpoint(struct fsl_mc_device *mc_dev,
}
EXPORT_SYMBOL_GPL(fsl_mc_get_endpoint);
static int parse_mc_ranges(struct device *dev,
int *paddr_cells,
int *mc_addr_cells,
int *mc_size_cells,
const __be32 **ranges_start)
{
const __be32 *prop;
int range_tuple_cell_count;
int ranges_len;
int tuple_len;
struct device_node *mc_node = dev->of_node;
*ranges_start = of_get_property(mc_node, "ranges", &ranges_len);
if (!(*ranges_start) || !ranges_len) {
dev_warn(dev,
"missing or empty ranges property for device tree node '%pOFn'\n",
mc_node);
return 0;
}
*paddr_cells = of_n_addr_cells(mc_node);
prop = of_get_property(mc_node, "#address-cells", NULL);
if (prop)
*mc_addr_cells = be32_to_cpup(prop);
else
*mc_addr_cells = *paddr_cells;
prop = of_get_property(mc_node, "#size-cells", NULL);
if (prop)
*mc_size_cells = be32_to_cpup(prop);
else
*mc_size_cells = of_n_size_cells(mc_node);
range_tuple_cell_count = *paddr_cells + *mc_addr_cells +
*mc_size_cells;
tuple_len = range_tuple_cell_count * sizeof(__be32);
if (ranges_len % tuple_len != 0) {
dev_err(dev, "malformed ranges property '%pOFn'\n", mc_node);
return -EINVAL;
}
return ranges_len / tuple_len;
}
static int get_mc_addr_translation_ranges(struct device *dev,
struct fsl_mc_addr_translation_range
**ranges,
u8 *num_ranges)
{
int ret;
int paddr_cells;
int mc_addr_cells;
int mc_size_cells;
int i;
const __be32 *ranges_start;
const __be32 *cell;
struct fsl_mc_addr_translation_range *r;
struct of_range_parser parser;
struct of_range range;
ret = parse_mc_ranges(dev,
&paddr_cells,
&mc_addr_cells,
&mc_size_cells,
&ranges_start);
if (ret < 0)
return ret;
*num_ranges = ret;
if (!ret) {
of_range_parser_init(&parser, dev->of_node);
*num_ranges = of_range_count(&parser);
if (!*num_ranges) {
/*
* Missing or empty ranges property ("ranges;") for the
* 'fsl,qoriq-mc' node. In this case, identity mapping
@ -1078,20 +1021,13 @@ static int get_mc_addr_translation_ranges(struct device *dev,
if (!(*ranges))
return -ENOMEM;
cell = ranges_start;
for (i = 0; i < *num_ranges; ++i) {
struct fsl_mc_addr_translation_range *range = &(*ranges)[i];
range->mc_region_type = of_read_number(cell, 1);
range->start_mc_offset = of_read_number(cell + 1,
mc_addr_cells - 1);
cell += mc_addr_cells;
range->start_phys_addr = of_read_number(cell, paddr_cells);
cell += paddr_cells;
range->end_mc_offset = range->start_mc_offset +
of_read_number(cell, mc_size_cells);
cell += mc_size_cells;
r = *ranges;
for_each_of_range(&parser, &range) {
r->mc_region_type = range.flags;
r->start_mc_offset = range.bus_addr;
r->end_mc_offset = range.bus_addr + range.size;
r->start_phys_addr = range.cpu_addr;
r++;
}
return 0;

2
drivers/bus/imx-weim.c
View file

@ -273,7 +273,7 @@ static int weim_probe(struct platform_device *pdev)
return -ENOMEM;
/* get the resource */
base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);

21
drivers/bus/omap_l3_smx.c
View file

@ -166,19 +166,10 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
irqreturn_t ret = IRQ_NONE;
int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
if (!int_type) {
if (!int_type)
status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
/*
* if we have a timeout error, there's nothing we can
* do besides rebooting the board. So let's BUG on any
* of such errors and handle the others. timeout error
* is severe and not expected to occur.
*/
BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
} else {
else
status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
/* No timeout error for debug sources */
}
/* identify the error source */
err_source = __ffs(status);
@ -190,6 +181,14 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
ret |= omap3_l3_block_irq(l3, error, error_addr);
}
/*
* if we have a timeout error, there's nothing we can
* do besides rebooting the board. So let's BUG on any
* of such errors and handle the others. timeout error
* is severe and not expected to occur.
*/
BUG_ON(!int_type && status & L3_STATUS_0_TIMEOUT_MASK);
/* Clear the status register */
clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
L3_AGENT_STATUS_CLEAR_TA;

4
drivers/bus/sunxi-rsb.c
View file

@ -746,7 +746,6 @@ static int sunxi_rsb_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct resource *r;
struct sunxi_rsb *rsb;
u32 clk_freq = 3000000;
int irq, ret;
@ -766,8 +765,7 @@ static int sunxi_rsb_probe(struct platform_device *pdev)
rsb->dev = dev;
rsb->clk_freq = clk_freq;
platform_set_drvdata(pdev, rsb);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rsb->regs = devm_ioremap_resource(dev, r);
rsb->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rsb->regs))
return PTR_ERR(rsb->regs);

4
drivers/bus/tegra-gmi.c
View file

@ -211,7 +211,6 @@ static int tegra_gmi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra_gmi *gmi;
struct resource *res;
int err;
gmi = devm_kzalloc(dev, sizeof(*gmi), GFP_KERNEL);
@ -221,8 +220,7 @@ static int tegra_gmi_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, gmi);
gmi->dev = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
gmi->base = devm_ioremap_resource(dev, res);
gmi->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(gmi->base))
return PTR_ERR(gmi->base);

5
drivers/bus/ti-sysc.c
View file

@ -109,6 +109,7 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = {
* @cookie: data used by legacy platform callbacks
* @name: name if available
* @revision: interconnect target module revision
* @sysconfig: saved sysconfig register value
* @reserved: target module is reserved and already in use
* @enabled: sysc runtime enabled status
* @needs_resume: runtime resume needed on resume from suspend
@ -1525,6 +1526,8 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff,
SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
/* Quirks that need to be set based on the module address */
SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
@ -3106,7 +3109,7 @@ static int sysc_init_static_data(struct sysc *ddata)
match = soc_device_match(sysc_soc_match);
if (match && match->data)
sysc_soc->soc = (int)match->data;
sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data;
/*
* Check and warn about possible old incomplete dtb. We now want to see

4
drivers/bus/vexpress-config.c
View file

@ -350,7 +350,6 @@ static struct vexpress_config_bridge_ops vexpress_syscfg_bridge_ops = {
static int vexpress_syscfg_probe(struct platform_device *pdev)
{
struct vexpress_syscfg *syscfg;
struct resource *res;
struct vexpress_config_bridge *bridge;
struct device_node *node;
int master;
@ -362,8 +361,7 @@ static int vexpress_syscfg_probe(struct platform_device *pdev)
syscfg->dev = &pdev->dev;
INIT_LIST_HEAD(&syscfg->funcs);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
syscfg->base = devm_ioremap_resource(&pdev->dev, res);
syscfg->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(syscfg->base))
return PTR_ERR(syscfg->base);

430
drivers/firmware/arm_scmi/perf.c
View file

@ -2,19 +2,22 @@
/*
* System Control and Management Interface (SCMI) Performance Protocol
*
* Copyright (C) 2018-2022 ARM Ltd.
* Copyright (C) 2018-2023 ARM Ltd.
*/
#define pr_fmt(fmt) "SCMI Notifications PERF - " fmt
#include <linux/bits.h>
#include <linux/of.h>
#include <linux/hashtable.h>
#include <linux/io.h>
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/scmi_protocol.h>
#include <linux/sort.h>
#include <linux/xarray.h>
#include <trace/events/scmi.h>
@ -46,6 +49,9 @@ struct scmi_opp {
u32 perf;
u32 power;
u32 trans_latency_us;
u32 indicative_freq;
u32 level_index;
struct hlist_node hash;
};
struct scmi_msg_resp_perf_attributes {
@ -66,6 +72,7 @@ struct scmi_msg_resp_perf_domain_attributes {
#define SUPPORTS_PERF_LEVEL_NOTIFY(x) ((x) & BIT(28))
#define SUPPORTS_PERF_FASTCHANNELS(x) ((x) & BIT(27))
#define SUPPORTS_EXTENDED_NAMES(x) ((x) & BIT(26))
#define SUPPORTS_LEVEL_INDEXING(x) ((x) & BIT(25))
__le32 rate_limit_us;
__le32 sustained_freq_khz;
__le32 sustained_perf_level;
@ -122,12 +129,27 @@ struct scmi_msg_resp_perf_describe_levels {
} opp[];
};
struct scmi_msg_resp_perf_describe_levels_v4 {
__le16 num_returned;
__le16 num_remaining;
struct {
__le32 perf_val;
__le32 power;
__le16 transition_latency_us;
__le16 reserved;
__le32 indicative_freq;
__le32 level_index;
} opp[];
};
struct perf_dom_info {
u32 id;
bool set_limits;
bool set_perf;
bool perf_limit_notify;
bool perf_level_notify;
bool perf_fastchannels;
bool level_indexing_mode;
u32 opp_count;
u32 sustained_freq_khz;
u32 sustained_perf_level;
@ -135,11 +157,26 @@ struct perf_dom_info {
char name[SCMI_MAX_STR_SIZE];
struct scmi_opp opp[MAX_OPPS];
struct scmi_fc_info *fc_info;
struct xarray opps_by_idx;
struct xarray opps_by_lvl;
DECLARE_HASHTABLE(opps_by_freq, ilog2(MAX_OPPS));
};
#define LOOKUP_BY_FREQ(__htp, __freq) \
({ \
/* u32 cast is needed to pick right hash func */ \
u32 f_ = (u32)(__freq); \
struct scmi_opp *_opp; \
\
hash_for_each_possible((__htp), _opp, hash, f_) \
if (_opp->indicative_freq == f_) \
break; \
_opp; \
})
struct scmi_perf_info {
u32 version;
int num_domains;
u16 num_domains;
enum scmi_power_scale power_scale;
u64 stats_addr;
u32 stats_size;
@ -186,9 +223,20 @@ static int scmi_perf_attributes_get(const struct scmi_protocol_handle *ph,
return ret;
}
static void scmi_perf_xa_destroy(void *data)
{
int domain;
struct scmi_perf_info *pinfo = data;
for (domain = 0; domain < pinfo->num_domains; domain++) {
xa_destroy(&((pinfo->dom_info + domain)->opps_by_idx));
xa_destroy(&((pinfo->dom_info + domain)->opps_by_lvl));
}
}
static int
scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph,
u32 domain, struct perf_dom_info *dom_info,
struct perf_dom_info *dom_info,
u32 version)
{
int ret;
@ -197,11 +245,11 @@ scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph,
struct scmi_msg_resp_perf_domain_attributes *attr;
ret = ph->xops->xfer_get_init(ph, PERF_DOMAIN_ATTRIBUTES,
sizeof(domain), sizeof(*attr), &t);
sizeof(dom_info->id), sizeof(*attr), &t);
if (ret)
return ret;
put_unaligned_le32(domain, t->tx.buf);
put_unaligned_le32(dom_info->id, t->tx.buf);
attr = t->rx.buf;
ret = ph->xops->do_xfer(ph, t);
@ -213,6 +261,9 @@ scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph,
dom_info->perf_limit_notify = SUPPORTS_PERF_LIMIT_NOTIFY(flags);
dom_info->perf_level_notify = SUPPORTS_PERF_LEVEL_NOTIFY(flags);
dom_info->perf_fastchannels = SUPPORTS_PERF_FASTCHANNELS(flags);
if (PROTOCOL_REV_MAJOR(version) >= 0x4)
dom_info->level_indexing_mode =
SUPPORTS_LEVEL_INDEXING(flags);
dom_info->sustained_freq_khz =
le32_to_cpu(attr->sustained_freq_khz);
dom_info->sustained_perf_level =
@ -236,8 +287,15 @@ scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph,
*/
if (!ret && PROTOCOL_REV_MAJOR(version) >= 0x3 &&
SUPPORTS_EXTENDED_NAMES(flags))
ph->hops->extended_name_get(ph, PERF_DOMAIN_NAME_GET, domain,
dom_info->name, SCMI_MAX_STR_SIZE);
ph->hops->extended_name_get(ph, PERF_DOMAIN_NAME_GET,
dom_info->id, dom_info->name,
SCMI_MAX_STR_SIZE);
if (dom_info->level_indexing_mode) {
xa_init(&dom_info->opps_by_idx);
xa_init(&dom_info->opps_by_lvl);
hash_init(dom_info->opps_by_freq);
}
return ret;
}
@ -250,7 +308,7 @@ static int opp_cmp_func(const void *opp1, const void *opp2)
}
struct scmi_perf_ipriv {
u32 domain;
u32 version;
struct perf_dom_info *perf_dom;
};
@ -261,7 +319,7 @@ static void iter_perf_levels_prepare_message(void *message,
struct scmi_msg_perf_describe_levels *msg = message;
const struct scmi_perf_ipriv *p = priv;
msg->domain = cpu_to_le32(p->domain);
msg->domain = cpu_to_le32(p->perf_dom->id);
/* Set the number of OPPs to be skipped/already read */
msg->level_index = cpu_to_le32(desc_index);
}
@ -277,31 +335,63 @@ static int iter_perf_levels_update_state(struct scmi_iterator_state *st,
return 0;
}
static inline void
process_response_opp(struct scmi_opp *opp, unsigned int loop_idx,
const struct scmi_msg_resp_perf_describe_levels *r)
{
opp->perf = le32_to_cpu(r->opp[loop_idx].perf_val);
opp->power = le32_to_cpu(r->opp[loop_idx].power);
opp->trans_latency_us =
le16_to_cpu(r->opp[loop_idx].transition_latency_us);
}
static inline void
process_response_opp_v4(struct perf_dom_info *dom, struct scmi_opp *opp,
unsigned int loop_idx,
const struct scmi_msg_resp_perf_describe_levels_v4 *r)
{
opp->perf = le32_to_cpu(r->opp[loop_idx].perf_val);
opp->power = le32_to_cpu(r->opp[loop_idx].power);
opp->trans_latency_us =
le16_to_cpu(r->opp[loop_idx].transition_latency_us);
/* Note that PERF v4 reports always five 32-bit words */
opp->indicative_freq = le32_to_cpu(r->opp[loop_idx].indicative_freq);
if (dom->level_indexing_mode) {
opp->level_index = le32_to_cpu(r->opp[loop_idx].level_index);
xa_store(&dom->opps_by_idx, opp->level_index, opp, GFP_KERNEL);
xa_store(&dom->opps_by_lvl, opp->perf, opp, GFP_KERNEL);
hash_add(dom->opps_by_freq, &opp->hash, opp->indicative_freq);
}
}
static int
iter_perf_levels_process_response(const struct scmi_protocol_handle *ph,
const void *response,
struct scmi_iterator_state *st, void *priv)
{
struct scmi_opp *opp;
const struct scmi_msg_resp_perf_describe_levels *r = response;
struct scmi_perf_ipriv *p = priv;
opp = &p->perf_dom->opp[st->desc_index + st->loop_idx];
opp->perf = le32_to_cpu(r->opp[st->loop_idx].perf_val);
opp->power = le32_to_cpu(r->opp[st->loop_idx].power);
opp->trans_latency_us =
le16_to_cpu(r->opp[st->loop_idx].transition_latency_us);
if (PROTOCOL_REV_MAJOR(p->version) <= 0x3)
process_response_opp(opp, st->loop_idx, response);
else
process_response_opp_v4(p->perf_dom, opp, st->loop_idx,
response);
p->perf_dom->opp_count++;
dev_dbg(ph->dev, "Level %d Power %d Latency %dus\n",
opp->perf, opp->power, opp->trans_latency_us);
dev_dbg(ph->dev, "Level %d Power %d Latency %dus Ifreq %d Index %d\n",
opp->perf, opp->power, opp->trans_latency_us,
opp->indicative_freq, opp->level_index);
return 0;
}
static int
scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, u32 domain,
struct perf_dom_info *perf_dom)
scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph,
struct perf_dom_info *perf_dom, u32 version)
{
int ret;
void *iter;
@ -311,7 +401,7 @@ scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, u32 domain,
.process_response = iter_perf_levels_process_response,
};
struct scmi_perf_ipriv ppriv = {
.domain = domain,
.version = version,
.perf_dom = perf_dom,
};
@ -333,8 +423,8 @@ scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, u32 domain,
return ret;
}
static int scmi_perf_mb_limits_set(const struct scmi_protocol_handle *ph,
u32 domain, u32 max_perf, u32 min_perf)
static int scmi_perf_msg_limits_set(const struct scmi_protocol_handle *ph,
u32 domain, u32 max_perf, u32 min_perf)
{
int ret;
struct scmi_xfer *t;
@ -356,31 +446,73 @@ static int scmi_perf_mb_limits_set(const struct scmi_protocol_handle *ph,
return ret;
}
static int scmi_perf_limits_set(const struct scmi_protocol_handle *ph,
u32 domain, u32 max_perf, u32 min_perf)
static inline struct perf_dom_info *
scmi_perf_domain_lookup(const struct scmi_protocol_handle *ph, u32 domain)
{
struct scmi_perf_info *pi = ph->get_priv(ph);
struct perf_dom_info *dom = pi->dom_info + domain;
if (PROTOCOL_REV_MAJOR(pi->version) >= 0x3 && !max_perf && !min_perf)
return -EINVAL;
if (domain >= pi->num_domains)
return ERR_PTR(-EINVAL);
return pi->dom_info + domain;
}
static int __scmi_perf_limits_set(const struct scmi_protocol_handle *ph,
struct perf_dom_info *dom, u32 max_perf,
u32 min_perf)
{
if (dom->fc_info && dom->fc_info[PERF_FC_LIMIT].set_addr) {
struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LIMIT];
trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LIMITS_SET,
domain, min_perf, max_perf);
dom->id, min_perf, max_perf);
iowrite32(max_perf, fci->set_addr);
iowrite32(min_perf, fci->set_addr + 4);
ph->hops->fastchannel_db_ring(fci->set_db);
return 0;
}
return scmi_perf_mb_limits_set(ph, domain, max_perf, min_perf);
return scmi_perf_msg_limits_set(ph, dom->id, max_perf, min_perf);
}
static int scmi_perf_mb_limits_get(const struct scmi_protocol_handle *ph,
u32 domain, u32 *max_perf, u32 *min_perf)
static int scmi_perf_limits_set(const struct scmi_protocol_handle *ph,
u32 domain, u32 max_perf, u32 min_perf)
{
struct scmi_perf_info *pi = ph->get_priv(ph);
struct perf_dom_info *dom;
dom = scmi_perf_domain_lookup(ph, domain);
if (IS_ERR(dom))
return PTR_ERR(dom);
if (PROTOCOL_REV_MAJOR(pi->version) >= 0x3 && !max_perf && !min_perf)
return -EINVAL;
if (dom->level_indexing_mode) {
struct scmi_opp *opp;
if (min_perf) {
opp = xa_load(&dom->opps_by_lvl, min_perf);
if (!opp)
return -EIO;
min_perf = opp->level_index;
}
if (max_perf) {
opp = xa_load(&dom->opps_by_lvl, max_perf);
if (!opp)
return -EIO;
max_perf = opp->level_index;
}
}
return __scmi_perf_limits_set(ph, dom, max_perf, min_perf);
}
static int scmi_perf_msg_limits_get(const struct scmi_protocol_handle *ph,
u32 domain, u32 *max_perf, u32 *min_perf)
{
int ret;
struct scmi_xfer *t;
@ -405,27 +537,58 @@ static int scmi_perf_mb_limits_get(const struct scmi_protocol_handle *ph,
return ret;
}
static int scmi_perf_limits_get(const struct scmi_protocol_handle *ph,
u32 domain, u32 *max_perf, u32 *min_perf)
static int __scmi_perf_limits_get(const struct scmi_protocol_handle *ph,
struct perf_dom_info *dom, u32 *max_perf,
u32 *min_perf)
{
struct scmi_perf_info *pi = ph->get_priv(ph);
struct perf_dom_info *dom = pi->dom_info + domain;
if (dom->fc_info && dom->fc_info[PERF_FC_LIMIT].get_addr) {
struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LIMIT];
*max_perf = ioread32(fci->get_addr);
*min_perf = ioread32(fci->get_addr + 4);
trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LIMITS_GET,
domain, *min_perf, *max_perf);
dom->id, *min_perf, *max_perf);
return 0;
}
return scmi_perf_mb_limits_get(ph, domain, max_perf, min_perf);
return scmi_perf_msg_limits_get(ph, dom->id, max_perf, min_perf);
}
static int scmi_perf_mb_level_set(const struct scmi_protocol_handle *ph,
u32 domain, u32 level, bool poll)
static int scmi_perf_limits_get(const struct scmi_protocol_handle *ph,
u32 domain, u32 *max_perf, u32 *min_perf)
{
int ret;
struct perf_dom_info *dom;
dom = scmi_perf_domain_lookup(ph, domain);
if (IS_ERR(dom))
return PTR_ERR(dom);
ret = __scmi_perf_limits_get(ph, dom, max_perf, min_perf);
if (ret)
return ret;
if (dom->level_indexing_mode) {
struct scmi_opp *opp;
opp = xa_load(&dom->opps_by_idx, *min_perf);
if (!opp)
return -EIO;
*min_perf = opp->perf;
opp = xa_load(&dom->opps_by_idx, *max_perf);
if (!opp)
return -EIO;
*max_perf = opp->perf;
}
return 0;
}
static int scmi_perf_msg_level_set(const struct scmi_protocol_handle *ph,
u32 domain, u32 level, bool poll)
{
int ret;
struct scmi_xfer *t;
@ -446,27 +609,47 @@ static int scmi_perf_mb_level_set(const struct scmi_protocol_handle *ph,
return ret;
}
static int scmi_perf_level_set(const struct scmi_protocol_handle *ph,
u32 domain, u32 level, bool poll)
static int __scmi_perf_level_set(const struct scmi_protocol_handle *ph,
struct perf_dom_info *dom, u32 level,
bool poll)
{
struct scmi_perf_info *pi = ph->get_priv(ph);
struct perf_dom_info *dom = pi->dom_info + domain;
if (dom->fc_info && dom->fc_info[PERF_FC_LEVEL].set_addr) {
struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LEVEL];
trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LEVEL_SET,
domain, level, 0);
dom->id, level, 0);
iowrite32(level, fci->set_addr);
ph->hops->fastchannel_db_ring(fci->set_db);
return 0;
}
return scmi_perf_mb_level_set(ph, domain, level, poll);
return scmi_perf_msg_level_set(ph, dom->id, level, poll);
}
static int scmi_perf_mb_level_get(const struct scmi_protocol_handle *ph,
u32 domain, u32 *level, bool poll)
static int scmi_perf_level_set(const struct scmi_protocol_handle *ph,
u32 domain, u32 level, bool poll)
{
struct perf_dom_info *dom;
dom = scmi_perf_domain_lookup(ph, domain);
if (IS_ERR(dom))
return PTR_ERR(dom);
if (dom->level_indexing_mode) {
struct scmi_opp *opp;
opp = xa_load(&dom->opps_by_lvl, level);
if (!opp)
return -EIO;
level = opp->level_index;
}
return __scmi_perf_level_set(ph, dom, level, poll);
}
static int scmi_perf_msg_level_get(const struct scmi_protocol_handle *ph,
u32 domain, u32 *level, bool poll)
{
int ret;
struct scmi_xfer *t;
@ -487,20 +670,45 @@ static int scmi_perf_mb_level_get(const struct scmi_protocol_handle *ph,
return ret;
}
static int scmi_perf_level_get(const struct scmi_protocol_handle *ph,
u32 domain, u32 *level, bool poll)
static int __scmi_perf_level_get(const struct scmi_protocol_handle *ph,
struct perf_dom_info *dom, u32 *level,
bool poll)
{
struct scmi_perf_info *pi = ph->get_priv(ph);
struct perf_dom_info *dom = pi->dom_info + domain;
if (dom->fc_info && dom->fc_info[PERF_FC_LEVEL].get_addr) {
*level = ioread32(dom->fc_info[PERF_FC_LEVEL].get_addr);
trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LEVEL_GET,
domain, *level, 0);
dom->id, *level, 0);
return 0;
}
return scmi_perf_mb_level_get(ph, domain, level, poll);
return scmi_perf_msg_level_get(ph, dom->id, level, poll);
}
static int scmi_perf_level_get(const struct scmi_protocol_handle *ph,
u32 domain, u32 *level, bool poll)
{
int ret;
struct perf_dom_info *dom;
dom = scmi_perf_domain_lookup(ph, domain);
if (IS_ERR(dom))
return PTR_ERR(dom);
ret = __scmi_perf_level_get(ph, dom, level, poll);
if (ret)
return ret;
if (dom->level_indexing_mode) {
struct scmi_opp *opp;
opp = xa_load(&dom->opps_by_idx, *level);
if (!opp)
return -EIO;
*level = opp->perf;
}
return 0;
}
static int scmi_perf_level_limits_notify(const struct scmi_protocol_handle *ph,
@ -574,27 +782,37 @@ static int scmi_dvfs_device_opps_add(const struct scmi_protocol_handle *ph,
unsigned long freq;
struct scmi_opp *opp;
struct perf_dom_info *dom;
struct scmi_perf_info *pi = ph->get_priv(ph);
domain = scmi_dev_domain_id(dev);
if (domain < 0)
return domain;
return -EINVAL;
dom = pi->dom_info + domain;
dom = scmi_perf_domain_lookup(ph, domain);
if (IS_ERR(dom))
return PTR_ERR(dom);
for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) {
freq = opp->perf * dom->mult_factor;
if (!dom->level_indexing_mode)
freq = opp->perf * dom->mult_factor;
else
freq = opp->indicative_freq * 1000;
ret = dev_pm_opp_add(dev, freq, 0);
if (ret) {
dev_warn(dev, "failed to add opp %luHz\n", freq);
while (idx-- > 0) {
freq = (--opp)->perf * dom->mult_factor;
if (!dom->level_indexing_mode)
freq = (--opp)->perf * dom->mult_factor;
else
freq = (--opp)->indicative_freq * 1000;
dev_pm_opp_remove(dev, freq);
}
return ret;
}
dev_dbg(dev, "[%d][%s]:: Registered OPP[%d] %lu\n",
domain, dom->name, idx, freq);
}
return 0;
}
@ -603,14 +821,17 @@ static int
scmi_dvfs_transition_latency_get(const struct scmi_protocol_handle *ph,
struct device *dev)
{
int domain;
struct perf_dom_info *dom;
struct scmi_perf_info *pi = ph->get_priv(ph);
int domain = scmi_dev_domain_id(dev);
domain = scmi_dev_domain_id(dev);
if (domain < 0)
return domain;
return -EINVAL;
dom = scmi_perf_domain_lookup(ph, domain);
if (IS_ERR(dom))
return PTR_ERR(dom);
dom = pi->dom_info + domain;
/* uS to nS */
return dom->opp[dom->opp_count - 1].trans_latency_us * 1000;
}
@ -618,10 +839,26 @@ scmi_dvfs_transition_latency_get(const struct scmi_protocol_handle *ph,
static int scmi_dvfs_freq_set(const struct scmi_protocol_handle *ph, u32 domain,
unsigned long freq, bool poll)
{
struct scmi_perf_info *pi = ph->get_priv(ph);
struct perf_dom_info *dom = pi->dom_info + domain;
unsigned int level;
struct perf_dom_info *dom;
return scmi_perf_level_set(ph, domain, freq / dom->mult_factor, poll);
dom = scmi_perf_domain_lookup(ph, domain);
if (IS_ERR(dom))
return PTR_ERR(dom);
if (!dom->level_indexing_mode) {
level = freq / dom->mult_factor;
} else {
struct scmi_opp *opp;
opp = LOOKUP_BY_FREQ(dom->opps_by_freq, freq / 1000);
if (!opp)
return -EIO;
level = opp->level_index;
}
return __scmi_perf_level_set(ph, dom, level, poll);
}
static int scmi_dvfs_freq_get(const struct scmi_protocol_handle *ph, u32 domain,
@ -629,12 +866,27 @@ static int scmi_dvfs_freq_get(const struct scmi_protocol_handle *ph, u32 domain,
{
int ret;
u32 level;
struct scmi_perf_info *pi = ph->get_priv(ph);
struct perf_dom_info *dom = pi->dom_info + domain;
struct perf_dom_info *dom;
ret = scmi_perf_level_get(ph, domain, &level, poll);
if (!ret)
dom = scmi_perf_domain_lookup(ph, domain);
if (IS_ERR(dom))
return PTR_ERR(dom);
ret = __scmi_perf_level_get(ph, dom, &level, poll);
if (ret)
return ret;
if (!dom->level_indexing_mode) {
*freq = level * dom->mult_factor;
} else {
struct scmi_opp *opp;
opp = xa_load(&dom->opps_by_idx, level);
if (!opp)
return -EIO;
*freq = opp->indicative_freq * 1000;
}
return ret;
}
@ -643,18 +895,21 @@ static int scmi_dvfs_est_power_get(const struct scmi_protocol_handle *ph,
u32 domain, unsigned long *freq,
unsigned long *power)
{
struct scmi_perf_info *pi = ph->get_priv(ph);
struct perf_dom_info *dom;
unsigned long opp_freq;
int idx, ret = -EINVAL;
struct scmi_opp *opp;
dom = pi->dom_info + domain;
if (!dom)
return -EIO;
dom = scmi_perf_domain_lookup(ph, domain);
if (IS_ERR(dom))
return PTR_ERR(dom);
for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) {
opp_freq = opp->perf * dom->mult_factor;
if (!dom->level_indexing_mode)
opp_freq = opp->perf * dom->mult_factor;
else
opp_freq = opp->indicative_freq * 1000;
if (opp_freq < *freq)
continue;
@ -670,10 +925,16 @@ static int scmi_dvfs_est_power_get(const struct scmi_protocol_handle *ph,
static bool scmi_fast_switch_possible(const struct scmi_protocol_handle *ph,
struct device *dev)
{
int domain;
struct perf_dom_info *dom;
struct scmi_perf_info *pi = ph->get_priv(ph);
dom = pi->dom_info + scmi_dev_domain_id(dev);
domain = scmi_dev_domain_id(dev);
if (domain < 0)
return false;
dom = scmi_perf_domain_lookup(ph, domain);
if (IS_ERR(dom))
return false;
return dom->fc_info && dom->fc_info[PERF_FC_LEVEL].set_addr;
}
@ -831,13 +1092,18 @@ static int scmi_perf_protocol_init(const struct scmi_protocol_handle *ph)
for (domain = 0; domain < pinfo->num_domains; domain++) {
struct perf_dom_info *dom = pinfo->dom_info + domain;
scmi_perf_domain_attributes_get(ph, domain, dom, version);
scmi_perf_describe_levels_get(ph, domain, dom);
dom->id = domain;
scmi_perf_domain_attributes_get(ph, dom, version);
scmi_perf_describe_levels_get(ph, dom, version);
if (dom->perf_fastchannels)
scmi_perf_domain_init_fc(ph, domain, &dom->fc_info);
scmi_perf_domain_init_fc(ph, dom->id, &dom->fc_info);
}
ret = devm_add_action_or_reset(ph->dev, scmi_perf_xa_destroy, pinfo);
if (ret)
return ret;
pinfo->version = version;
return ph->set_priv(ph, pinfo);

118
drivers/firmware/imx/imx-scu-irq.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Copyright 2019,2023 NXP
*
* Implementation of the SCU IRQ functions using MU.
*
@ -9,12 +9,14 @@
#include <dt-bindings/firmware/imx/rsrc.h>
#include <linux/firmware/imx/ipc.h>
#include <linux/firmware/imx/sci.h>
#include <linux/kobject.h>
#include <linux/mailbox_client.h>
#include <linux/suspend.h>
#include <linux/sysfs.h>
#define IMX_SC_IRQ_FUNC_ENABLE 1
#define IMX_SC_IRQ_FUNC_STATUS 2
#define IMX_SC_IRQ_NUM_GROUP 4
#define IMX_SC_IRQ_NUM_GROUP 9
static u32 mu_resource_id;
@ -40,63 +42,102 @@ struct imx_sc_msg_irq_enable {
u8 enable;
} __packed;
struct scu_wakeup {
u32 mask;
u32 wakeup_src;
bool valid;
};
/* Sysfs functions */
static struct kobject *wakeup_obj;
static ssize_t wakeup_source_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf);
static struct kobj_attribute wakeup_source_attr =
__ATTR(wakeup_src, 0660, wakeup_source_show, NULL);
static struct scu_wakeup scu_irq_wakeup[IMX_SC_IRQ_NUM_GROUP];
static struct imx_sc_ipc *imx_sc_irq_ipc_handle;
static struct work_struct imx_sc_irq_work;
static ATOMIC_NOTIFIER_HEAD(imx_scu_irq_notifier_chain);
static BLOCKING_NOTIFIER_HEAD(imx_scu_irq_notifier_chain);
int imx_scu_irq_register_notifier(struct notifier_block *nb)
{
return atomic_notifier_chain_register(
return blocking_notifier_chain_register(
&imx_scu_irq_notifier_chain, nb);
}
EXPORT_SYMBOL(imx_scu_irq_register_notifier);
int imx_scu_irq_unregister_notifier(struct notifier_block *nb)
{
return atomic_notifier_chain_unregister(
return blocking_notifier_chain_unregister(
&imx_scu_irq_notifier_chain, nb);
}
EXPORT_SYMBOL(imx_scu_irq_unregister_notifier);
static int imx_scu_irq_notifier_call_chain(unsigned long status, u8 *group)
{
return atomic_notifier_call_chain(&imx_scu_irq_notifier_chain,
return blocking_notifier_call_chain(&imx_scu_irq_notifier_chain,
status, (void *)group);
}
static void imx_scu_irq_work_handler(struct work_struct *work)
{
struct imx_sc_msg_irq_get_status msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
u32 irq_status;
int ret;
u8 i;
for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) {
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_IRQ;
hdr->func = IMX_SC_IRQ_FUNC_STATUS;
hdr->size = 2;
if (scu_irq_wakeup[i].mask) {
scu_irq_wakeup[i].valid = false;
scu_irq_wakeup[i].wakeup_src = 0;
}
msg.data.req.resource = mu_resource_id;
msg.data.req.group = i;
ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true);
ret = imx_scu_irq_get_status(i, &irq_status);
if (ret) {
pr_err("get irq group %d status failed, ret %d\n",
i, ret);
return;
}
irq_status = msg.data.resp.status;
if (!irq_status)
continue;
if (scu_irq_wakeup[i].mask & irq_status) {
scu_irq_wakeup[i].valid = true;
scu_irq_wakeup[i].wakeup_src = irq_status & scu_irq_wakeup[i].mask;
} else {
scu_irq_wakeup[i].wakeup_src = irq_status;
}
pm_system_wakeup();
imx_scu_irq_notifier_call_chain(irq_status, &i);
}
}
int imx_scu_irq_get_status(u8 group, u32 *irq_status)
{
struct imx_sc_msg_irq_get_status msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
int ret;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_IRQ;
hdr->func = IMX_SC_IRQ_FUNC_STATUS;
hdr->size = 2;
msg.data.req.resource = mu_resource_id;
msg.data.req.group = group;
ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true);
if (ret)
return ret;
if (irq_status)
*irq_status = msg.data.resp.status;
return 0;
}
EXPORT_SYMBOL(imx_scu_irq_get_status);
int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable)
{
struct imx_sc_msg_irq_enable msg;
@ -121,6 +162,11 @@ int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable)
pr_err("enable irq failed, group %d, mask %d, ret %d\n",
group, mask, ret);
if (enable)
scu_irq_wakeup[group].mask |= mask;
else
scu_irq_wakeup[group].mask &= ~mask;
return ret;
}
EXPORT_SYMBOL(imx_scu_irq_group_enable);
@ -130,6 +176,25 @@ static void imx_scu_irq_callback(struct mbox_client *c, void *msg)
schedule_work(&imx_sc_irq_work);
}
static ssize_t wakeup_source_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
{
int i;
for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) {
if (!scu_irq_wakeup[i].wakeup_src)
continue;
if (scu_irq_wakeup[i].valid)
sprintf(buf, "Wakeup source group = %d, irq = 0x%x\n",
i, scu_irq_wakeup[i].wakeup_src);
else
sprintf(buf, "Spurious SCU wakeup, group = %d, irq = 0x%x\n",
i, scu_irq_wakeup[i].wakeup_src);
}
return strlen(buf);
}
int imx_scu_enable_general_irq_channel(struct device *dev)
{
struct of_phandle_args spec;
@ -169,6 +234,25 @@ int imx_scu_enable_general_irq_channel(struct device *dev)
mu_resource_id = IMX_SC_R_MU_0A + i;
/* Create directory under /sysfs/firmware */
wakeup_obj = kobject_create_and_add("scu_wakeup_source", firmware_kobj);
if (!wakeup_obj) {
ret = -ENOMEM;
goto free_ch;
}
ret = sysfs_create_file(wakeup_obj, &wakeup_source_attr.attr);
if (ret) {
dev_err(dev, "Cannot create wakeup source src file......\n");
kobject_put(wakeup_obj);
goto free_ch;
}
return 0;
free_ch:
mbox_free_channel(ch);
return ret;
}
EXPORT_SYMBOL(imx_scu_enable_general_irq_channel);

20
drivers/firmware/imx/imx-scu-soc.c
View file

@ -78,6 +78,22 @@ static int imx_scu_soc_id(void)
return msg.data.resp.id;
}
static const char *imx_scu_soc_name(u32 id)
{
switch (id) {
case 0x1:
return "i.MX8QM";
case 0x2:
return "i.MX8QXP";
case 0xe:
return "i.MX8DXL";
default:
break;
}
return "NULL";
}
int imx_scu_soc_init(struct device *dev)
{
struct soc_device_attribute *soc_dev_attr;
@ -113,9 +129,7 @@ int imx_scu_soc_init(struct device *dev)
/* format soc_id value passed from SCU firmware */
val = id & 0x1f;
soc_dev_attr->soc_id = devm_kasprintf(dev, GFP_KERNEL, "0x%x", val);
if (!soc_dev_attr->soc_id)
return -ENOMEM;
soc_dev_attr->soc_id = imx_scu_soc_name(val);
/* format revision value passed from SCU firmware */
val = (id >> 5) & 0xf;

9
drivers/firmware/imx/imx-scu.c
View file

@ -20,7 +20,7 @@
#include <linux/platform_device.h>
#define SCU_MU_CHAN_NUM 8
#define MAX_RX_TIMEOUT (msecs_to_jiffies(30))
#define MAX_RX_TIMEOUT (msecs_to_jiffies(3000))
struct imx_sc_chan {
struct imx_sc_ipc *sc_ipc;
@ -353,7 +353,12 @@ static struct platform_driver imx_scu_driver = {
},
.probe = imx_scu_probe,
};
builtin_platform_driver(imx_scu_driver);
static int __init imx_scu_driver_init(void)
{
return platform_driver_register(&imx_scu_driver);
}
subsys_initcall_sync(imx_scu_driver_init);
MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
MODULE_DESCRIPTION("IMX SCU firmware protocol driver");

2
drivers/firmware/meson/meson_sm.c
View file

@ -292,6 +292,8 @@ static int __init meson_sm_probe(struct platform_device *pdev)
return -ENOMEM;
chip = of_match_device(meson_sm_ids, dev)->data;
if (!chip)
return -EINVAL;
if (chip->cmd_shmem_in_base) {
fw->sm_shmem_in_base = meson_sm_map_shmem(chip->cmd_shmem_in_base,

158
drivers/firmware/qcom_scm.c
View file

@ -26,10 +26,6 @@
static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
module_param(download_mode, bool, 0);
#define SCM_HAS_CORE_CLK BIT(0)
#define SCM_HAS_IFACE_CLK BIT(1)
#define SCM_HAS_BUS_CLK BIT(2)
struct qcom_scm {
struct device *dev;
struct clk *core_clk;
@ -351,7 +347,7 @@ int qcom_scm_set_warm_boot_addr(void *entry)
return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_warm_bits);
return 0;
}
EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
EXPORT_SYMBOL_GPL(qcom_scm_set_warm_boot_addr);
/**
* qcom_scm_set_cold_boot_addr() - Set the cold boot address for all cpus
@ -364,7 +360,7 @@ int qcom_scm_set_cold_boot_addr(void *entry)
return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_cold_bits);
return 0;
}
EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
EXPORT_SYMBOL_GPL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@ -386,7 +382,7 @@ void qcom_scm_cpu_power_down(u32 flags)
qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_cpu_power_down);
EXPORT_SYMBOL_GPL(qcom_scm_cpu_power_down);
int qcom_scm_set_remote_state(u32 state, u32 id)
{
@ -405,7 +401,7 @@ int qcom_scm_set_remote_state(u32 state, u32 id)
return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_set_remote_state);
EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state);
static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
{
@ -515,7 +511,7 @@ out:
return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_pas_init_image);
EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image);
/**
* qcom_scm_pas_metadata_release() - release metadata context
@ -532,7 +528,7 @@ void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx)
ctx->phys = 0;
ctx->size = 0;
}
EXPORT_SYMBOL(qcom_scm_pas_metadata_release);
EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release);
/**
* qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
@ -571,7 +567,7 @@ int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup);
/**
* qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
@ -606,7 +602,7 @@ int qcom_scm_pas_auth_and_reset(u32 peripheral)
return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset);
/**
* qcom_scm_pas_shutdown() - Shut down the remote processor
@ -641,7 +637,7 @@ int qcom_scm_pas_shutdown(u32 peripheral)
return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_pas_shutdown);
EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown);
/**
* qcom_scm_pas_supported() - Check if the peripheral authentication service is
@ -670,7 +666,7 @@ bool qcom_scm_pas_supported(u32 peripheral)
return ret ? false : !!res.result[0];
}
EXPORT_SYMBOL(qcom_scm_pas_supported);
EXPORT_SYMBOL_GPL(qcom_scm_pas_supported);
static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
{
@ -732,7 +728,7 @@ int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
return ret < 0 ? ret : 0;
}
EXPORT_SYMBOL(qcom_scm_io_readl);
EXPORT_SYMBOL_GPL(qcom_scm_io_readl);
int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
{
@ -747,7 +743,7 @@ int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_io_writel);
EXPORT_SYMBOL_GPL(qcom_scm_io_writel);
/**
* qcom_scm_restore_sec_cfg_available() - Check if secure environment
@ -760,7 +756,7 @@ bool qcom_scm_restore_sec_cfg_available(void)
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,
QCOM_SCM_MP_RESTORE_SEC_CFG);
}
EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available);
EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg_available);
int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
{
@ -779,7 +775,7 @@ int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_restore_sec_cfg);
EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg);
int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
{
@ -800,7 +796,7 @@ int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
return ret ? : res.result[1];
}
EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size);
EXPORT_SYMBOL_GPL(qcom_scm_iommu_secure_ptbl_size);
int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
{
@ -824,7 +820,7 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
return ret;
}
EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
EXPORT_SYMBOL_GPL(qcom_scm_iommu_secure_ptbl_init);
int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size)
{
@ -839,7 +835,7 @@ int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size)
return qcom_scm_call(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_iommu_set_cp_pool_size);
EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_cp_pool_size);
int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
u32 cp_nonpixel_start,
@ -863,7 +859,7 @@ int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_mem_protect_video_var);
EXPORT_SYMBOL_GPL(qcom_scm_mem_protect_video_var);
static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
size_t mem_sz, phys_addr_t src, size_t src_sz,
@ -972,7 +968,7 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
*srcvm = next_vm;
return 0;
}
EXPORT_SYMBOL(qcom_scm_assign_mem);
EXPORT_SYMBOL_GPL(qcom_scm_assign_mem);
/**
* qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
@ -982,7 +978,7 @@ bool qcom_scm_ocmem_lock_available(void)
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM,
QCOM_SCM_OCMEM_LOCK_CMD);
}
EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock_available);
/**
* qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
@ -1008,7 +1004,7 @@ int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
return qcom_scm_call(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_ocmem_lock);
EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock);
/**
* qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
@ -1031,7 +1027,7 @@ int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size)
return qcom_scm_call(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
EXPORT_SYMBOL_GPL(qcom_scm_ocmem_unlock);
/**
* qcom_scm_ice_available() - Is the ICE key programming interface available?
@ -1046,7 +1042,7 @@ bool qcom_scm_ice_available(void)
__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
QCOM_SCM_ES_CONFIG_SET_ICE_KEY);
}
EXPORT_SYMBOL(qcom_scm_ice_available);
EXPORT_SYMBOL_GPL(qcom_scm_ice_available);
/**
* qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key
@ -1072,7 +1068,7 @@ int qcom_scm_ice_invalidate_key(u32 index)
return qcom_scm_call(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_ice_invalidate_key);
EXPORT_SYMBOL_GPL(qcom_scm_ice_invalidate_key);
/**
* qcom_scm_ice_set_key() - Set an inline encryption key
@ -1138,7 +1134,7 @@ int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
dma_free_coherent(__scm->dev, key_size, keybuf, key_phys);
return ret;
}
EXPORT_SYMBOL(qcom_scm_ice_set_key);
EXPORT_SYMBOL_GPL(qcom_scm_ice_set_key);
/**
* qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
@ -1160,7 +1156,7 @@ bool qcom_scm_hdcp_available(void)
return avail;
}
EXPORT_SYMBOL(qcom_scm_hdcp_available);
EXPORT_SYMBOL_GPL(qcom_scm_hdcp_available);
/**
* qcom_scm_hdcp_req() - Send HDCP request.
@ -1207,7 +1203,7 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
return ret;
}
EXPORT_SYMBOL(qcom_scm_hdcp_req);
EXPORT_SYMBOL_GPL(qcom_scm_hdcp_req);
int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt)
{
@ -1223,7 +1219,7 @@ int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt)
return qcom_scm_call(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_iommu_set_pt_format);
EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_pt_format);
int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
{
@ -1239,13 +1235,13 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
EXPORT_SYMBOL_GPL(qcom_scm_qsmmu500_wait_safe_toggle);
bool qcom_scm_lmh_dcvsh_available(void)
{
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH);
}
EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available);
EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh_available);
int qcom_scm_lmh_profile_change(u32 profile_id)
{
@ -1259,7 +1255,7 @@ int qcom_scm_lmh_profile_change(u32 profile_id)
return qcom_scm_call(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_lmh_profile_change);
EXPORT_SYMBOL_GPL(qcom_scm_lmh_profile_change);
int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
u64 limit_node, u32 node_id, u64 version)
@ -1297,7 +1293,7 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
dma_free_coherent(__scm->dev, payload_size, payload_buf, payload_phys);
return ret;
}
EXPORT_SYMBOL(qcom_scm_lmh_dcvsh);
EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh);
static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
{
@ -1332,7 +1328,7 @@ bool qcom_scm_is_available(void)
{
return !!__scm;
}
EXPORT_SYMBOL(qcom_scm_is_available);
EXPORT_SYMBOL_GPL(qcom_scm_is_available);
static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx)
{
@ -1405,7 +1401,6 @@ out:
static int qcom_scm_probe(struct platform_device *pdev)
{
struct qcom_scm *scm;
unsigned long clks;
int irq, ret;
scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
@ -1418,51 +1413,22 @@ static int qcom_scm_probe(struct platform_device *pdev)
mutex_init(&scm->scm_bw_lock);
clks = (unsigned long)of_device_get_match_data(&pdev->dev);
scm->path = devm_of_icc_get(&pdev->dev, NULL);
if (IS_ERR(scm->path))
return dev_err_probe(&pdev->dev, PTR_ERR(scm->path),
"failed to acquire interconnect path\n");
scm->core_clk = devm_clk_get(&pdev->dev, "core");
if (IS_ERR(scm->core_clk)) {
if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER)
return PTR_ERR(scm->core_clk);
scm->core_clk = devm_clk_get_optional(&pdev->dev, "core");
if (IS_ERR(scm->core_clk))
return PTR_ERR(scm->core_clk);
if (clks & SCM_HAS_CORE_CLK) {
dev_err(&pdev->dev, "failed to acquire core clk\n");
return PTR_ERR(scm->core_clk);
}
scm->iface_clk = devm_clk_get_optional(&pdev->dev, "iface");
if (IS_ERR(scm->iface_clk))
return PTR_ERR(scm->iface_clk);
scm->core_clk = NULL;
}
scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
if (IS_ERR(scm->iface_clk)) {
if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER)
return PTR_ERR(scm->iface_clk);
if (clks & SCM_HAS_IFACE_CLK) {
dev_err(&pdev->dev, "failed to acquire iface clk\n");
return PTR_ERR(scm->iface_clk);
}
scm->iface_clk = NULL;
}
scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
if (IS_ERR(scm->bus_clk)) {
if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER)
return PTR_ERR(scm->bus_clk);
if (clks & SCM_HAS_BUS_CLK) {
dev_err(&pdev->dev, "failed to acquire bus clk\n");
return PTR_ERR(scm->bus_clk);
}
scm->bus_clk = NULL;
}
scm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
if (IS_ERR(scm->bus_clk))
return PTR_ERR(scm->bus_clk);
scm->reset.ops = &qcom_scm_pas_reset_ops;
scm->reset.nr_resets = 1;
@ -1512,39 +1478,15 @@ static void qcom_scm_shutdown(struct platform_device *pdev)
}
static const struct of_device_id qcom_scm_dt_match[] = {
{ .compatible = "qcom,scm-apq8064",
/* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
},
{ .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK |
SCM_HAS_IFACE_CLK |
SCM_HAS_BUS_CLK)
},
{ .compatible = "qcom,scm-ipq4019" },
{ .compatible = "qcom,scm-mdm9607", .data = (void *)(SCM_HAS_CORE_CLK |
SCM_HAS_IFACE_CLK |
SCM_HAS_BUS_CLK) },
{ .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
{ .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
{ .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |
SCM_HAS_IFACE_CLK |
SCM_HAS_BUS_CLK)
},
{ .compatible = "qcom,scm-msm8953", .data = (void *)(SCM_HAS_CORE_CLK |
SCM_HAS_IFACE_CLK |
SCM_HAS_BUS_CLK)
},
{ .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK |
SCM_HAS_IFACE_CLK |
SCM_HAS_BUS_CLK)
},
{ .compatible = "qcom,scm-msm8976", .data = (void *)(SCM_HAS_CORE_CLK |
SCM_HAS_IFACE_CLK |
SCM_HAS_BUS_CLK)
},
{ .compatible = "qcom,scm-msm8994" },
{ .compatible = "qcom,scm-msm8996" },
{ .compatible = "qcom,scm-sm6375", .data = (void *)SCM_HAS_CORE_CLK },
{ .compatible = "qcom,scm" },
/* Legacy entries kept for backwards compatibility */
{ .compatible = "qcom,scm-apq8064" },
{ .compatible = "qcom,scm-apq8084" },
{ .compatible = "qcom,scm-ipq4019" },
{ .compatible = "qcom,scm-msm8953" },
{ .compatible = "qcom,scm-msm8974" },
{ .compatible = "qcom,scm-msm8996" },
{}
};
MODULE_DEVICE_TABLE(of, qcom_scm_dt_match);

49
drivers/firmware/ti_sci.c
View file

@ -97,7 +97,6 @@ struct ti_sci_desc {
* @node: list head
* @host_id: Host ID
* @users: Number of users of this instance
* @is_suspending: Flag set to indicate in suspend path.
*/
struct ti_sci_info {
struct device *dev;
@ -116,7 +115,6 @@ struct ti_sci_info {
u8 host_id;
/* protected by ti_sci_list_mutex */
int users;
bool is_suspending;
};
#define cl_to_ti_sci_info(c) container_of(c, struct ti_sci_info, cl)
@ -418,14 +416,14 @@ static inline int ti_sci_do_xfer(struct ti_sci_info *info,
ret = 0;
if (!info->is_suspending) {
if (system_state <= SYSTEM_RUNNING) {
/* And we wait for the response. */
timeout = msecs_to_jiffies(info->desc->max_rx_timeout_ms);
if (!wait_for_completion_timeout(&xfer->done, timeout))
ret = -ETIMEDOUT;
} else {
/*
* If we are suspending, we cannot use wait_for_completion_timeout
* If we are !running, we cannot use wait_for_completion_timeout
* during noirq phase, so we must manually poll the completion.
*/
ret = read_poll_timeout_atomic(try_wait_for_completion, done_state,
@ -1978,8 +1976,6 @@ static int ti_sci_free_irq(const struct ti_sci_handle *handle, u32 valid_params,
* @src_index: IRQ source index within the source device
* @dst_id: Device ID of the IRQ destination
* @dst_host_irq: IRQ number of the destination device
* @vint_irq: Boolean specifying if this interrupt belongs to
* Interrupt Aggregator.
*
* Return: 0 if all went fine, else return appropriate error.
*/
@ -2026,8 +2022,6 @@ static int ti_sci_cmd_set_event_map(const struct ti_sci_handle *handle,
* @src_index: IRQ source index within the source device
* @dst_id: Device ID of the IRQ destination
* @dst_host_irq: IRQ number of the destination device
* @vint_irq: Boolean specifying if this interrupt belongs to
* Interrupt Aggregator.
*
* Return: 0 if all went fine, else return appropriate error.
*/
@ -2620,6 +2614,7 @@ fail:
* configuration flags
* @handle: Pointer to TI SCI handle
* @proc_id: Processor ID this request is for
* @bootvector: Processor Boot vector (start address)
* @config_flags_set: Configuration flags to be set
* @config_flags_clear: Configuration flags to be cleared.
*
@ -2736,9 +2731,13 @@ fail:
}
/**
* ti_sci_cmd_get_boot_status() - Command to get the processor boot status
* ti_sci_cmd_proc_get_status() - Command to get the processor boot status
* @handle: Pointer to TI SCI handle
* @proc_id: Processor ID this request is for
* @bv: Processor Boot vector (start address)
* @cfg_flags: Processor specific configuration flags
* @ctrl_flags: Processor specific control flags
* @sts_flags: Processor specific status flags
*
* Return: 0 if all went well, else returns appropriate error value.
*/
@ -3256,7 +3255,7 @@ EXPORT_SYMBOL_GPL(devm_ti_sci_get_of_resource);
* @handle: TISCI handle
* @dev: Device pointer to which the resource is assigned
* @dev_id: TISCI device id to which the resource is assigned
* @suub_type: TISCI resource subytpe representing the resource.
* @sub_type: TISCI resource subytpe representing the resource.
*
* Return: Pointer to ti_sci_resource if all went well else appropriate
* error pointer.
@ -3281,35 +3280,6 @@ static int tisci_reboot_handler(struct notifier_block *nb, unsigned long mode,
return NOTIFY_BAD;
}
static void ti_sci_set_is_suspending(struct ti_sci_info *info, bool is_suspending)
{
info->is_suspending = is_suspending;
}
static int ti_sci_suspend(struct device *dev)
{
struct ti_sci_info *info = dev_get_drvdata(dev);
/*
* We must switch operation to polled mode now as drivers and the genpd
* layer may make late TI SCI calls to change clock and device states
* from the noirq phase of suspend.
*/
ti_sci_set_is_suspending(info, true);
return 0;
}
static int ti_sci_resume(struct device *dev)
{
struct ti_sci_info *info = dev_get_drvdata(dev);
ti_sci_set_is_suspending(info, false);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(ti_sci_pm_ops, ti_sci_suspend, ti_sci_resume);
/* Description for K2G */
static const struct ti_sci_desc ti_sci_pmmc_k2g_desc = {
.default_host_id = 2,
@ -3516,7 +3486,6 @@ static struct platform_driver ti_sci_driver = {
.driver = {
.name = "ti-sci",
.of_match_table = of_match_ptr(ti_sci_of_match),
.pm = &ti_sci_pm_ops,
},
};
module_platform_driver(ti_sci_driver);

3
drivers/genpd/amlogic/meson-ee-pwrc.c
View file

@ -4,13 +4,12 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/bitfield.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/reset-controller.h>
#include <linux/reset.h>
#include <linux/clk.h>

3
drivers/genpd/amlogic/meson-gx-pwrc-vpu.c
View file

@ -5,13 +5,12 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/bitfield.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/reset.h>
#include <linux/clk.h>
#include <linux/module.h>

30
drivers/genpd/amlogic/meson-secure-pwrc.c
View file

@ -7,10 +7,11 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <dt-bindings/power/meson-a1-power.h>
#include <dt-bindings/power/amlogic,c3-pwrc.h>
#include <dt-bindings/power/meson-s4-power.h>
#include <linux/arm-smccc.h>
#include <linux/firmware/meson/meson_sm.h>
@ -120,6 +121,22 @@ static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = {
SEC_PD(RSA, 0),
};
static struct meson_secure_pwrc_domain_desc c3_pwrc_domains[] = {
SEC_PD(C3_NNA, 0),
SEC_PD(C3_AUDIO, GENPD_FLAG_ALWAYS_ON),
SEC_PD(C3_SDIOA, GENPD_FLAG_ALWAYS_ON),
SEC_PD(C3_EMMC, GENPD_FLAG_ALWAYS_ON),
SEC_PD(C3_USB_COMB, GENPD_FLAG_ALWAYS_ON),
SEC_PD(C3_SDCARD, GENPD_FLAG_ALWAYS_ON),
SEC_PD(C3_ETH, GENPD_FLAG_ALWAYS_ON),
SEC_PD(C3_GE2D, GENPD_FLAG_ALWAYS_ON),
SEC_PD(C3_CVE, GENPD_FLAG_ALWAYS_ON),
SEC_PD(C3_GDC_WRAP, GENPD_FLAG_ALWAYS_ON),
SEC_PD(C3_ISP_TOP, GENPD_FLAG_ALWAYS_ON),
SEC_PD(C3_MIPI_ISP_WRAP, GENPD_FLAG_ALWAYS_ON),
SEC_PD(C3_VCODEC, 0),
};
static struct meson_secure_pwrc_domain_desc s4_pwrc_domains[] = {
SEC_PD(S4_DOS_HEVC, 0),
SEC_PD(S4_DOS_VDEC, 0),
@ -179,7 +196,7 @@ static int meson_secure_pwrc_probe(struct platform_device *pdev)
for (i = 0 ; i < match->count ; ++i) {
struct meson_secure_pwrc_domain *dom = &pwrc->domains[i];
if (!match->domains[i].index)
if (!match->domains[i].name)
continue;
dom->pwrc = pwrc;
@ -202,6 +219,11 @@ static struct meson_secure_pwrc_domain_data meson_secure_a1_pwrc_data = {
.count = ARRAY_SIZE(a1_pwrc_domains),
};
static struct meson_secure_pwrc_domain_data amlogic_secure_c3_pwrc_data = {
.domains = c3_pwrc_domains,
.count = ARRAY_SIZE(c3_pwrc_domains),
};
static struct meson_secure_pwrc_domain_data meson_secure_s4_pwrc_data = {
.domains = s4_pwrc_domains,
.count = ARRAY_SIZE(s4_pwrc_domains),
@ -212,6 +234,10 @@ static const struct of_device_id meson_secure_pwrc_match_table[] = {
.compatible = "amlogic,meson-a1-pwrc",
.data = &meson_secure_a1_pwrc_data,
},
{
.compatible = "amlogic,c3-pwrc",
.data = &amlogic_secure_c3_pwrc_data,
},
{
.compatible = "amlogic,meson-s4-pwrc",
.data = &meson_secure_s4_pwrc_data,

1
drivers/genpd/bcm/bcm-pmb.c
View file

@ -8,7 +8,6 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/reset/bcm63xx_pmb.h>

1
drivers/genpd/bcm/bcm63xx-power.c
View file

@ -14,7 +14,6 @@
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/of.h>
#include <linux/of_device.h>
struct bcm63xx_power_dev {
struct generic_pm_domain genpd;

2
drivers/genpd/bcm/raspberrypi-power.c
View file

@ -7,7 +7,7 @@
*/
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <dt-bindings/power/raspberrypi-power.h>

2
drivers/genpd/imx/gpcv2.c
View file

@ -9,7 +9,7 @@
*/
#include <linux/clk.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

3
drivers/genpd/imx/imx8m-blk-ctrl.c
View file

@ -8,7 +8,8 @@
#include <linux/device.h>
#include <linux/interconnect.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

2
drivers/genpd/imx/imx8mp-blk-ctrl.c
View file

@ -10,7 +10,7 @@
#include <linux/device.h>
#include <linux/interconnect.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

17
drivers/genpd/imx/imx93-blk-ctrl.c
View file

@ -6,7 +6,7 @@
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
@ -187,6 +187,8 @@ static int imx93_blk_ctrl_power_off(struct generic_pm_domain *genpd)
return 0;
}
static struct lock_class_key blk_ctrl_genpd_lock_class;
static int imx93_blk_ctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@ -269,6 +271,19 @@ static int imx93_blk_ctrl_probe(struct platform_device *pdev)
goto cleanup_pds;
}
/*
* We use runtime PM to trigger power on/off of the upstream GPC
* domain, as a strict hierarchical parent/child power domain
* setup doesn't allow us to meet the sequencing requirements.
* This means we have nested locking of genpd locks, without the
* nesting being visible at the genpd level, so we need a
* separate lock class to make lockdep aware of the fact that
* this are separate domain locks that can be nested without a
* self-deadlock.
*/
lockdep_set_class(&domain->genpd.mlock,
&blk_ctrl_genpd_lock_class);
bc->onecell_data.domains[i] = &domain->genpd;
}

2
drivers/genpd/imx/imx93-pd.c
View file

@ -5,8 +5,8 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/of_device.h>
#include <linux/iopoll.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>

1
drivers/genpd/qcom/cpr.c
View file

@ -15,7 +15,6 @@
#include <linux/bitops.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_opp.h>

118
drivers/genpd/qcom/rpmhpd.c
View file

@ -9,12 +9,12 @@
#include <linux/pm_domain.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <soc/qcom/cmd-db.h>
#include <soc/qcom/rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#define domain_to_rpmhpd(domain) container_of(domain, struct rpmhpd, pd)
@ -307,6 +307,21 @@ static const struct rpmhpd_desc sdx65_desc = {
.num_pds = ARRAY_SIZE(sdx65_rpmhpds),
};
/* SDX75 RPMH powerdomains */
static struct rpmhpd *sdx75_rpmhpds[] = {
[RPMHPD_CX] = &cx,
[RPMHPD_CX_AO] = &cx_ao,
[RPMHPD_MSS] = &mss,
[RPMHPD_MX] = &mx,
[RPMHPD_MX_AO] = &mx_ao,
[RPMHPD_MXC] = &mxc,
};
static const struct rpmhpd_desc sdx75_desc = {
.rpmhpds = sdx75_rpmhpds,
.num_pds = ARRAY_SIZE(sdx75_rpmhpds),
};
/* SM6350 RPMH powerdomains */
static struct rpmhpd *sm6350_rpmhpds[] = {
[SM6350_CX] = &cx_w_mx_parent,
@ -359,16 +374,16 @@ static const struct rpmhpd_desc sa8155p_desc = {
/* SM8250 RPMH powerdomains */
static struct rpmhpd *sm8250_rpmhpds[] = {
[SM8250_CX] = &cx_w_mx_parent,
[SM8250_CX_AO] = &cx_ao_w_mx_parent,
[SM8250_EBI] = &ebi,
[SM8250_GFX] = &gfx,
[SM8250_LCX] = &lcx,
[SM8250_LMX] = &lmx,
[SM8250_MMCX] = &mmcx,
[SM8250_MMCX_AO] = &mmcx_ao,
[SM8250_MX] = &mx,
[SM8250_MX_AO] = &mx_ao,
[RPMHPD_CX] = &cx_w_mx_parent,
[RPMHPD_CX_AO] = &cx_ao_w_mx_parent,
[RPMHPD_EBI] = &ebi,
[RPMHPD_GFX] = &gfx,
[RPMHPD_LCX] = &lcx,
[RPMHPD_LMX] = &lmx,
[RPMHPD_MMCX] = &mmcx,
[RPMHPD_MMCX_AO] = &mmcx_ao,
[RPMHPD_MX] = &mx,
[RPMHPD_MX_AO] = &mx_ao,
};
static const struct rpmhpd_desc sm8250_desc = {
@ -378,19 +393,19 @@ static const struct rpmhpd_desc sm8250_desc = {
/* SM8350 Power domains */
static struct rpmhpd *sm8350_rpmhpds[] = {
[SM8350_CX] = &cx_w_mx_parent,
[SM8350_CX_AO] = &cx_ao_w_mx_parent,
[SM8350_EBI] = &ebi,
[SM8350_GFX] = &gfx,
[SM8350_LCX] = &lcx,
[SM8350_LMX] = &lmx,
[SM8350_MMCX] = &mmcx,
[SM8350_MMCX_AO] = &mmcx_ao,
[SM8350_MSS] = &mss,
[SM8350_MX] = &mx,
[SM8350_MX_AO] = &mx_ao,
[SM8350_MXC] = &mxc,
[SM8350_MXC_AO] = &mxc_ao,
[RPMHPD_CX] = &cx_w_mx_parent,
[RPMHPD_CX_AO] = &cx_ao_w_mx_parent,
[RPMHPD_EBI] = &ebi,
[RPMHPD_GFX] = &gfx,
[RPMHPD_LCX] = &lcx,
[RPMHPD_LMX] = &lmx,
[RPMHPD_MMCX] = &mmcx,
[RPMHPD_MMCX_AO] = &mmcx_ao,
[RPMHPD_MSS] = &mss,
[RPMHPD_MX] = &mx,
[RPMHPD_MX_AO] = &mx_ao,
[RPMHPD_MXC] = &mxc,
[RPMHPD_MXC_AO] = &mxc_ao,
};
static const struct rpmhpd_desc sm8350_desc = {
@ -400,19 +415,19 @@ static const struct rpmhpd_desc sm8350_desc = {
/* SM8450 RPMH powerdomains */
static struct rpmhpd *sm8450_rpmhpds[] = {
[SM8450_CX] = &cx,
[SM8450_CX_AO] = &cx_ao,
[SM8450_EBI] = &ebi,
[SM8450_GFX] = &gfx,
[SM8450_LCX] = &lcx,
[SM8450_LMX] = &lmx,
[SM8450_MMCX] = &mmcx_w_cx_parent,
[SM8450_MMCX_AO] = &mmcx_ao_w_cx_parent,
[SM8450_MSS] = &mss,
[SM8450_MX] = &mx,
[SM8450_MX_AO] = &mx_ao,
[SM8450_MXC] = &mxc,
[SM8450_MXC_AO] = &mxc_ao,
[RPMHPD_CX] = &cx,
[RPMHPD_CX_AO] = &cx_ao,
[RPMHPD_EBI] = &ebi,
[RPMHPD_GFX] = &gfx,
[RPMHPD_LCX] = &lcx,
[RPMHPD_LMX] = &lmx,
[RPMHPD_MMCX] = &mmcx_w_cx_parent,
[RPMHPD_MMCX_AO] = &mmcx_ao_w_cx_parent,
[RPMHPD_MSS] = &mss,
[RPMHPD_MX] = &mx,
[RPMHPD_MX_AO] = &mx_ao,
[RPMHPD_MXC] = &mxc,
[RPMHPD_MXC_AO] = &mxc_ao,
};
static const struct rpmhpd_desc sm8450_desc = {
@ -422,20 +437,20 @@ static const struct rpmhpd_desc sm8450_desc = {
/* SM8550 RPMH powerdomains */
static struct rpmhpd *sm8550_rpmhpds[] = {
[SM8550_CX] = &cx,
[SM8550_CX_AO] = &cx_ao,
[SM8550_EBI] = &ebi,
[SM8550_GFX] = &gfx,
[SM8550_LCX] = &lcx,
[SM8550_LMX] = &lmx,
[SM8550_MMCX] = &mmcx_w_cx_parent,
[SM8550_MMCX_AO] = &mmcx_ao_w_cx_parent,
[SM8550_MSS] = &mss,
[SM8550_MX] = &mx,
[SM8550_MX_AO] = &mx_ao,
[SM8550_MXC] = &mxc,
[SM8550_MXC_AO] = &mxc_ao,
[SM8550_NSP] = &nsp,
[RPMHPD_CX] = &cx,
[RPMHPD_CX_AO] = &cx_ao,
[RPMHPD_EBI] = &ebi,
[RPMHPD_GFX] = &gfx,
[RPMHPD_LCX] = &lcx,
[RPMHPD_LMX] = &lmx,
[RPMHPD_MMCX] = &mmcx_w_cx_parent,
[RPMHPD_MMCX_AO] = &mmcx_ao_w_cx_parent,
[RPMHPD_MSS] = &mss,
[RPMHPD_MX] = &mx,
[RPMHPD_MX_AO] = &mx_ao,
[RPMHPD_MXC] = &mxc,
[RPMHPD_MXC_AO] = &mxc_ao,
[RPMHPD_NSP] = &nsp,
};
static const struct rpmhpd_desc sm8550_desc = {
@ -545,6 +560,7 @@ static const struct of_device_id rpmhpd_match_table[] = {
{ .compatible = "qcom,sdm845-rpmhpd", .data = &sdm845_desc },
{ .compatible = "qcom,sdx55-rpmhpd", .data = &sdx55_desc},
{ .compatible = "qcom,sdx65-rpmhpd", .data = &sdx65_desc},
{ .compatible = "qcom,sdx75-rpmhpd", .data = &sdx75_desc},
{ .compatible = "qcom,sm6350-rpmhpd", .data = &sm6350_desc },
{ .compatible = "qcom,sm8150-rpmhpd", .data = &sm8150_desc },
{ .compatible = "qcom,sm8250-rpmhpd", .data = &sm8250_desc },

35
drivers/genpd/qcom/rpmpd.c
View file

@ -8,7 +8,6 @@
#include <linux/mutex.h>
#include <linux/pm_domain.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/soc/qcom/smd-rpm.h>
@ -58,6 +57,7 @@ struct rpmpd {
struct qcom_smd_rpm *rpm;
unsigned int max_state;
__le32 key;
bool state_synced;
};
struct rpmpd_desc {
@ -823,7 +823,11 @@ static int rpmpd_aggregate_corner(struct rpmpd *pd)
unsigned int this_active_corner = 0, this_sleep_corner = 0;
unsigned int peer_active_corner = 0, peer_sleep_corner = 0;
to_active_sleep(pd, pd->corner, &this_active_corner, &this_sleep_corner);
/* Clamp to the highest corner/level if sync_state isn't done yet */
if (!pd->state_synced)
this_active_corner = this_sleep_corner = pd->max_state - 1;
else
to_active_sleep(pd, pd->corner, &this_active_corner, &this_sleep_corner);
if (peer && peer->enabled)
to_active_sleep(peer, peer->corner, &peer_active_corner,
@ -973,11 +977,38 @@ static int rpmpd_probe(struct platform_device *pdev)
return of_genpd_add_provider_onecell(pdev->dev.of_node, data);
}
static void rpmpd_sync_state(struct device *dev)
{
const struct rpmpd_desc *desc = of_device_get_match_data(dev);
struct rpmpd **rpmpds = desc->rpmpds;
struct rpmpd *pd;
unsigned int i;
int ret;
mutex_lock(&rpmpd_lock);
for (i = 0; i < desc->num_pds; i++) {
pd = rpmpds[i];
if (!pd)
continue;
pd->state_synced = true;
if (!pd->enabled)
pd->corner = 0;
ret = rpmpd_aggregate_corner(pd);
if (ret)
dev_err(dev, "failed to sync %s: %d\n", pd->pd.name, ret);
}
mutex_unlock(&rpmpd_lock);
}
static struct platform_driver rpmpd_driver = {
.driver = {
.name = "qcom-rpmpd",
.of_match_table = rpmpd_match_table,
.suppress_bind_attrs = true,
.sync_state = rpmpd_sync_state,
},
.probe = rpmpd_probe,
};

1
drivers/genpd/rockchip/pm-domains.c
View file

@ -976,6 +976,7 @@ static const struct rockchip_domain_info px30_pm_domains[] = {
static const struct rockchip_domain_info rv1126_pm_domains[] = {
[RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
[RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
[RV1126_PD_VO] = DOMAIN_RV1126("vo", BIT(5), BIT(7), BIT(7), false),
[RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
[RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
[RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),

3
drivers/genpd/samsung/exynos-pm-domains.c
View file

@ -11,11 +11,12 @@
#include <linux/io.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/pm_domain.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
struct exynos_pm_domain_config {

13
drivers/genpd/ti/omap_prm.c
View file

@ -13,7 +13,6 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
@ -943,10 +942,6 @@ static int omap_prm_probe(struct platform_device *pdev)
struct omap_prm *prm;
int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
data = of_device_get_match_data(&pdev->dev);
if (!data)
return -ENOTSUPP;
@ -955,6 +950,10 @@ static int omap_prm_probe(struct platform_device *pdev)
if (!prm)
return -ENOMEM;
prm->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(prm->base))
return PTR_ERR(prm->base);
while (data->base != res->start) {
if (!data->base)
return -EINVAL;
@ -963,10 +962,6 @@ static int omap_prm_probe(struct platform_device *pdev)
prm->data = data;
prm->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(prm->base))
return PTR_ERR(prm->base);
ret = omap_prm_domain_init(&pdev->dev, prm);
if (ret)
return ret;

1
drivers/irqchip/irq-versatile-fpga.c
View file

@ -242,5 +242,4 @@ static int __init fpga_irq_of_init(struct device_node *node,
}
IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init);
IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init);
IRQCHIP_DECLARE(ox810se_rps, "oxsemi,ox810se-rps-irq", fpga_irq_of_init);
#endif

3
drivers/memory/brcmstb_dpfe.c
View file

@ -32,8 +32,7 @@
#include <linux/firmware.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#define DRVNAME "brcmstb-dpfe"

1
drivers/memory/da8xx-ddrctl.c
View file

@ -10,7 +10,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/io.h>

2
drivers/memory/fsl_ifc.c
View file

@ -15,7 +15,7 @@
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/fsl_ifc.h>
#include <linux/irqdomain.h>

1
drivers/memory/jz4780-nemc.c
View file

@ -12,7 +12,6 @@
#include <linux/math64.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

1
drivers/memory/pl353-smc.c
View file

@ -10,6 +10,7 @@
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>

1
drivers/memory/renesas-rpc-if.c
View file

@ -13,7 +13,6 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>

2
drivers/memory/samsung/exynos5422-dmc.c
View file

@ -13,7 +13,7 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

2
drivers/memory/stm32-fmc2-ebi.c
View file

@ -7,8 +7,10 @@
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>

2
drivers/memory/tegra/mc.c
View file

@ -11,7 +11,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sort.h>

2
drivers/memory/tegra/tegra124.c
View file

@ -4,7 +4,7 @@
*/
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <dt-bindings/memory/tegra124-mc.h>

136
drivers/memory/tegra/tegra186-emc.c
View file

@ -155,6 +155,73 @@ DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops,
tegra186_emc_debug_max_rate_get,
tegra186_emc_debug_max_rate_set, "%llu\n");
static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc)
{
struct mrq_emc_dvfs_latency_response response;
struct tegra_bpmp_message msg;
unsigned int i;
int err;
memset(&msg, 0, sizeof(msg));
msg.mrq = MRQ_EMC_DVFS_LATENCY;
msg.tx.data = NULL;
msg.tx.size = 0;
msg.rx.data = &response;
msg.rx.size = sizeof(response);
err = tegra_bpmp_transfer(emc->bpmp, &msg);
if (err < 0) {
dev_err(emc->dev, "failed to EMC DVFS pairs: %d\n", err);
return err;
}
if (msg.rx.ret < 0) {
dev_err(emc->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret);
return -EINVAL;
}
emc->debugfs.min_rate = ULONG_MAX;
emc->debugfs.max_rate = 0;
emc->num_dvfs = response.num_pairs;
emc->dvfs = devm_kmalloc_array(emc->dev, emc->num_dvfs, sizeof(*emc->dvfs), GFP_KERNEL);
if (!emc->dvfs)
return -ENOMEM;
dev_dbg(emc->dev, "%u DVFS pairs:\n", emc->num_dvfs);
for (i = 0; i < emc->num_dvfs; i++) {
emc->dvfs[i].rate = response.pairs[i].freq * 1000;
emc->dvfs[i].latency = response.pairs[i].latency;
if (emc->dvfs[i].rate < emc->debugfs.min_rate)
emc->debugfs.min_rate = emc->dvfs[i].rate;
if (emc->dvfs[i].rate > emc->debugfs.max_rate)
emc->debugfs.max_rate = emc->dvfs[i].rate;
dev_dbg(emc->dev, " %2u: %lu Hz -> %lu us\n", i,
emc->dvfs[i].rate, emc->dvfs[i].latency);
}
err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, emc->debugfs.max_rate);
if (err < 0) {
dev_err(emc->dev, "failed to set rate range [%lu-%lu] for %pC\n",
emc->debugfs.min_rate, emc->debugfs.max_rate, emc->clk);
return err;
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
&tegra186_emc_debug_available_rates_fops);
debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc,
&tegra186_emc_debug_min_rate_fops);
debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc,
&tegra186_emc_debug_max_rate_fops);
return 0;
}
/*
* tegra_emc_icc_set_bw() - Set BW api for EMC provider
* @src: ICC node for External Memory Controller (EMC)
@ -251,10 +318,7 @@ err_msg:
static int tegra186_emc_probe(struct platform_device *pdev)
{
struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent);
struct mrq_emc_dvfs_latency_response response;
struct tegra_bpmp_message msg;
struct tegra186_emc *emc;
unsigned int i;
int err;
emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
@ -275,69 +339,11 @@ static int tegra186_emc_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, emc);
emc->dev = &pdev->dev;
memset(&msg, 0, sizeof(msg));
msg.mrq = MRQ_EMC_DVFS_LATENCY;
msg.tx.data = NULL;
msg.tx.size = 0;
msg.rx.data = &response;
msg.rx.size = sizeof(response);
err = tegra_bpmp_transfer(emc->bpmp, &msg);
if (err < 0) {
dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err);
goto put_bpmp;
if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) {
err = tegra186_emc_get_emc_dvfs_latency(emc);
if (err)
goto put_bpmp;
}
if (msg.rx.ret < 0) {
err = -EINVAL;
dev_err(&pdev->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret);
goto put_bpmp;
}
emc->debugfs.min_rate = ULONG_MAX;
emc->debugfs.max_rate = 0;
emc->num_dvfs = response.num_pairs;
emc->dvfs = devm_kmalloc_array(&pdev->dev, emc->num_dvfs,
sizeof(*emc->dvfs), GFP_KERNEL);
if (!emc->dvfs) {
err = -ENOMEM;
goto put_bpmp;
}
dev_dbg(&pdev->dev, "%u DVFS pairs:\n", emc->num_dvfs);
for (i = 0; i < emc->num_dvfs; i++) {
emc->dvfs[i].rate = response.pairs[i].freq * 1000;
emc->dvfs[i].latency = response.pairs[i].latency;
if (emc->dvfs[i].rate < emc->debugfs.min_rate)
emc->debugfs.min_rate = emc->dvfs[i].rate;
if (emc->dvfs[i].rate > emc->debugfs.max_rate)
emc->debugfs.max_rate = emc->dvfs[i].rate;
dev_dbg(&pdev->dev, " %2u: %lu Hz -> %lu us\n", i,
emc->dvfs[i].rate, emc->dvfs[i].latency);
}
err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
emc->debugfs.max_rate);
if (err < 0) {
dev_err(&pdev->dev,
"failed to set rate range [%lu-%lu] for %pC\n",
emc->debugfs.min_rate, emc->debugfs.max_rate,
emc->clk);
goto put_bpmp;
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root,
emc, &tegra186_emc_debug_available_rates_fops);
debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root,
emc, &tegra186_emc_debug_min_rate_fops);
debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root,
emc, &tegra186_emc_debug_max_rate_fops);
if (mc && mc->soc->icc_ops) {
if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) {

3
drivers/memory/tegra/tegra186.c
View file

@ -7,7 +7,8 @@
#include <linux/iommu.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <soc/tegra/mc.h>

3
drivers/memory/tegra/tegra20.c
View file

@ -5,8 +5,9 @@
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/string.h>

4
drivers/memory/tegra/tegra210-emc-core.c
View file

@ -9,10 +9,10 @@
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_reserved_mem.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/thermal.h>
#include <soc/tegra/fuse.h>

620
drivers/memory/tegra/tegra234.c
View file

@ -12,6 +12,10 @@
#include <soc/tegra/bpmp.h>
#include "mc.h"
/*
* MC Client entries are sorted in the increasing order of the
* override and security register offsets.
*/
static const struct tegra_mc_client tegra234_mc_clients[] = {
{
.id = TEGRA234_MEMORY_CLIENT_HDAR,
@ -25,6 +29,130 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0xac,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVENCSRD,
.name = "nvencsrd",
.bpmp_id = TEGRA_ICC_BPMP_NVENC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVENC,
.regs = {
.sid = {
.override = 0xe0,
.security = 0xe4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
.name = "pcie6ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE6,
.regs = {
.sid = {
.override = 0x140,
.security = 0x144,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
.name = "pcie6aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE6,
.regs = {
.sid = {
.override = 0x148,
.security = 0x14c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
.name = "pcie7ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE7,
.regs = {
.sid = {
.override = 0x150,
.security = 0x154,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVENCSWR,
.name = "nvencswr",
.bpmp_id = TEGRA_ICC_BPMP_NVENC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVENC,
.regs = {
.sid = {
.override = 0x158,
.security = 0x15c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
.name = "dla0rdb",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x160,
.security = 0x164,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
.name = "dla0rdb1",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x168,
.security = 0x16c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
.name = "dla0wrb",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x170,
.security = 0x174,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
.name = "dla0rdb",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x178,
.security = 0x17c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
.name = "pcie7aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE7,
.regs = {
.sid = {
.override = 0x180,
.security = 0x184,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
.name = "pcie8ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE8,
.regs = {
.sid = {
.override = 0x190,
.security = 0x194,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_HDAW,
.name = "hdaw",
@ -37,6 +165,102 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x1ac,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
.name = "pcie8aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE8,
.regs = {
.sid = {
.override = 0x1d8,
.security = 0x1dc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
.name = "pcie9ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE9,
.regs = {
.sid = {
.override = 0x1e0,
.security = 0x1e4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
.name = "pcie6ar1",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE6,
.regs = {
.sid = {
.override = 0x1e8,
.security = 0x1ec,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
.name = "pcie9aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE9,
.regs = {
.sid = {
.override = 0x1f0,
.security = 0x1f4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
.name = "pcie10ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE10,
.regs = {
.sid = {
.override = 0x1f8,
.security = 0x1fc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
.name = "pcie10aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE10,
.regs = {
.sid = {
.override = 0x200,
.security = 0x204,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
.name = "pcie10ar1",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE10,
.regs = {
.sid = {
.override = 0x240,
.security = 0x244,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
.name = "pcie7ar1",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE7,
.regs = {
.sid = {
.override = 0x248,
.security = 0x24c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_MGBEARD,
.name = "mgbeard",
@ -157,6 +381,50 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x33c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_VICSRD,
.name = "vicsrd",
.bpmp_id = TEGRA_ICC_BPMP_VIC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_VIC,
.regs = {
.sid = {
.override = 0x360,
.security = 0x364,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_VICSWR,
.name = "vicswr",
.bpmp_id = TEGRA_ICC_BPMP_VIC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_VIC,
.regs = {
.sid = {
.override = 0x368,
.security = 0x36c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
.name = "dla0rdb1",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x370,
.security = 0x374,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
.name = "dla0wrb",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x378,
.security = 0x37c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_VI2W,
.name = "vi2w",
@ -182,15 +450,27 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_VI2FALW,
.name = "vi2falw",
.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
.type = TEGRA_ICC_ISO_VIFAL,
.sid = TEGRA234_SID_ISO_VI2FALC,
.id = TEGRA234_MEMORY_CLIENT_NVDECSRD,
.name = "nvdecsrd",
.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDEC,
.regs = {
.sid = {
.override = 0x3e0,
.security = 0x3e4,
.override = 0x3c0,
.security = 0x3c4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVDECSWR,
.name = "nvdecswr",
.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDEC,
.regs = {
.sid = {
.override = 0x3c8,
.security = 0x3cc,
},
},
}, {
@ -217,6 +497,42 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x3dc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_VI2FALW,
.name = "vi2falw",
.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
.type = TEGRA_ICC_ISO_VIFAL,
.sid = TEGRA234_SID_ISO_VI2FALC,
.regs = {
.sid = {
.override = 0x3e0,
.security = 0x3e4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVJPGSRD,
.name = "nvjpgsrd",
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVJPG,
.regs = {
.sid = {
.override = 0x3f0,
.security = 0x3f4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVJPGSWR,
.name = "nvjpgswr",
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVJPG,
.regs = {
.sid = {
.override = 0x3f8,
.security = 0x3fc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
.name = "nvdisplayr",
@ -229,18 +545,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x494,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
.name = "nvdisplayr1",
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
.type = TEGRA_ICC_ISO_DISPLAY,
.sid = TEGRA234_SID_ISO_NVDISPLAY,
.regs = {
.sid = {
.override = 0x508,
.security = 0x50c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_BPMPR,
.name = "bpmpr",
@ -305,6 +609,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x504,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
.name = "nvdisplayr1",
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
.type = TEGRA_ICC_ISO_DISPLAY,
.sid = TEGRA234_SID_ISO_NVDISPLAY,
.regs = {
.sid = {
.override = 0x508,
.security = 0x50c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
.name = "dla0rda",
@ -335,26 +651,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x604,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
.name = "dla0rdb",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x160,
.security = 0x164,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
.name = "dla0rda1",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x748,
.security = 0x74c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
.name = "dla0falwrb",
@ -365,26 +661,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x60c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
.name = "dla0rdb1",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x168,
.security = 0x16c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
.name = "dla0wrb",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x170,
.security = 0x174,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA,
.name = "dla0rda",
@ -415,26 +691,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x624,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
.name = "dla0rdb",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x178,
.security = 0x17c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
.name = "dla0rda1",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x750,
.security = 0x754,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
.name = "dla0falwrb",
@ -445,26 +701,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x62c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
.name = "dla0rdb1",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x370,
.security = 0x374,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
.name = "dla0wrb",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x378,
.security = 0x37c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE0R,
.name = "pcie0r",
@ -609,6 +845,26 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x71c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
.name = "dla0rda1",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x748,
.security = 0x74c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
.name = "dla0rda1",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x750,
.security = 0x754,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
.name = "pcie5r1",
@ -622,159 +878,27 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
.name = "pcie6ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
.id = TEGRA234_MEMORY_CLIENT_NVJPG1SRD,
.name = "nvjpg1srd",
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE6,
.sid = TEGRA234_SID_NVJPG1,
.regs = {
.sid = {
.override = 0x140,
.security = 0x144,
.override = 0x918,
.security = 0x91c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
.name = "pcie6aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
.id = TEGRA234_MEMORY_CLIENT_NVJPG1SWR,
.name = "nvjpg1swr",
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE6,
.sid = TEGRA234_SID_NVJPG1,
.regs = {
.sid = {
.override = 0x148,
.security = 0x14c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
.name = "pcie6ar1",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE6,
.regs = {
.sid = {
.override = 0x1e8,
.security = 0x1ec,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
.name = "pcie7ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE7,
.regs = {
.sid = {
.override = 0x150,
.security = 0x154,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
.name = "pcie7aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE7,
.regs = {
.sid = {
.override = 0x180,
.security = 0x184,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
.name = "pcie7ar1",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE7,
.regs = {
.sid = {
.override = 0x248,
.security = 0x24c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
.name = "pcie8ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE8,
.regs = {
.sid = {
.override = 0x190,
.security = 0x194,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
.name = "pcie8aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE8,
.regs = {
.sid = {
.override = 0x1d8,
.security = 0x1dc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
.name = "pcie9ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE9,
.regs = {
.sid = {
.override = 0x1e0,
.security = 0x1e4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
.name = "pcie9aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE9,
.regs = {
.sid = {
.override = 0x1f0,
.security = 0x1f4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
.name = "pcie10ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE10,
.regs = {
.sid = {
.override = 0x1f8,
.security = 0x1fc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
.name = "pcie10aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE10,
.regs = {
.sid = {
.override = 0x200,
.security = 0x204,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
.name = "pcie10ar1",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE10,
.regs = {
.sid = {
.override = 0x240,
.security = 0x244,
.override = 0x920,
.security = 0x924,
},
},
}, {
@ -792,6 +916,16 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.name = "sw_cluster2",
.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2,
.type = TEGRA_ICC_NISO,
}, {
.id = TEGRA234_MEMORY_CLIENT_NVL1R,
.name = "nvl1r",
.bpmp_id = TEGRA_ICC_BPMP_GPU,
.type = TEGRA_ICC_NISO,
}, {
.id = TEGRA234_MEMORY_CLIENT_NVL1W,
.name = "nvl1w",
.bpmp_id = TEGRA_ICC_BPMP_GPU,
.type = TEGRA_ICC_NISO,
},
};

2
drivers/memory/tegra/tegra30-emc.c
View file

@ -22,7 +22,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_platform.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>

2
drivers/memory/tegra/tegra30.c
View file

@ -3,8 +3,8 @@
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <dt-bindings/memory/tegra30-mc.h>

5
drivers/net/ipa/ipa_power.c
View file

@ -324,15 +324,12 @@ void ipa_power_retention(struct ipa *ipa, bool enable)
{
static const char fmt[] = "{ class: bcm, res: ipa_pc, val: %c }";
struct ipa_power *power = ipa->power;
char buf[36]; /* Exactly enough for fmt[]; size a multiple of 4 */
int ret;
if (!power->qmp)
return; /* Not needed on this platform */
(void)snprintf(buf, sizeof(buf), fmt, enable ? '1' : '0');
ret = qmp_send(power->qmp, buf, sizeof(buf));
ret = qmp_send(power->qmp, fmt, enable ? '1' : '0');
if (ret)
dev_err(power->dev, "error %d sending QMP %sable request\n",
ret, enable ? "en" : "dis");

8
drivers/remoteproc/qcom_q6v5.c
View file

@ -23,19 +23,13 @@
static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable)
{
char buf[Q6V5_LOAD_STATE_MSG_LEN];
int ret;
if (!q6v5->qmp)
return 0;
ret = snprintf(buf, sizeof(buf),
"{class: image, res: load_state, name: %s, val: %s}",
ret = qmp_send(q6v5->qmp, "{class: image, res: load_state, name: %s, val: %s}",
q6v5->load_state, enable ? "on" : "off");
WARN_ON(ret >= Q6V5_LOAD_STATE_MSG_LEN);
ret = qmp_send(q6v5->qmp, buf, sizeof(buf));
if (ret)
dev_err(q6v5->dev, "failed to toggle load state\n");

1
drivers/reset/hisilicon/hi6220_reset.c
View file

@ -13,7 +13,6 @@
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/reset-controller.h>

6
drivers/reset/hisilicon/reset-hi3660.c
View file

@ -6,7 +6,7 @@
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
@ -90,8 +90,8 @@ static int hi3660_reset_probe(struct platform_device *pdev)
"hisi,rst-syscon");
}
if (IS_ERR(rc->map)) {
dev_err(dev, "failed to get hisilicon,rst-syscon\n");
return PTR_ERR(rc->map);
return dev_err_probe(dev, PTR_ERR(rc->map),
"failed to get hisilicon,rst-syscon\n");
}
rc->rst.ops = &hi3660_reset_ops,

2
drivers/reset/reset-ath79.c
View file

@ -93,8 +93,6 @@ static int ath79_reset_probe(struct platform_device *pdev)
if (!ath79_reset)
return -ENOMEM;
platform_set_drvdata(pdev, ath79_reset);
ath79_reset->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ath79_reset->base))
return PTR_ERR(ath79_reset->base);

2
drivers/reset/reset-bcm6345.c
View file

@ -102,8 +102,6 @@ static int bcm6345_reset_probe(struct platform_device *pdev)
if (!bcm6345_reset)
return -ENOMEM;
platform_set_drvdata(pdev, bcm6345_reset);
bcm6345_reset->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(bcm6345_reset->base))
return PTR_ERR(bcm6345_reset->base);

2
drivers/reset/reset-imx7.c
View file

@ -9,7 +9,7 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/regmap.h>

2
drivers/reset/reset-intel-gw.c
View file

@ -6,7 +6,7 @@
#include <linux/bitfield.h>
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/regmap.h>

1
drivers/reset/reset-k210.c
View file

@ -3,7 +3,6 @@
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
*/
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/delay.h>

1
drivers/reset/reset-lantiq.c
View file

@ -173,7 +173,6 @@ static int lantiq_rcu_reset_probe(struct platform_device *pdev)
return -ENOMEM;
priv->dev = &pdev->dev;
platform_set_drvdata(pdev, priv);
err = lantiq_rcu_reset_of_parse(pdev, priv);
if (err)

2
drivers/reset/reset-lpc18xx.c
View file

@ -188,8 +188,6 @@ static int lpc18xx_rgu_probe(struct platform_device *pdev)
rc->rcdev.ops = &lpc18xx_rgu_ops;
rc->rcdev.of_node = pdev->dev.of_node;
platform_set_drvdata(pdev, rc);
ret = reset_controller_register(&rc->rcdev);
if (ret) {
dev_err(&pdev->dev, "unable to register device\n");

3
drivers/reset/reset-meson-audio-arb.c
View file

@ -5,7 +5,8 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/spinlock.h>

3
drivers/reset/reset-meson.c
View file

@ -14,7 +14,6 @@
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/of_device.h>
#define BITS_PER_REG 32
@ -129,8 +128,6 @@ static int meson_reset_probe(struct platform_device *pdev)
if (!data->param)
return -ENODEV;
platform_set_drvdata(pdev, data);
spin_lock_init(&data->lock);
data->rcdev.owner = THIS_MODULE;

3
drivers/reset/reset-microchip-sparx5.c
View file

@ -7,9 +7,10 @@
* https://github.com/microchip-ung/sparx-5_reginfo
*/
#include <linux/mfd/syscon.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>

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