382 lines
9.9 KiB
C
382 lines
9.9 KiB
C
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/*
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* QSpan pci routines.
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* Most 8xx boards use the QSpan PCI bridge. The config address register
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* is located 0x500 from the base of the bridge control/status registers.
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* The data register is located at 0x504.
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* This is a two step operation. First, the address register is written,
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* then the data register is read/written as required.
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* I don't know what to do about interrupts (yet).
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*
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* The RPX Classic implementation shares a chip select for normal
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* PCI access and QSpan control register addresses. The selection is
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* further selected by a bit setting in a board control register.
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* Although it should happen, we disable interrupts during this operation
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* to make sure some driver doesn't accidentally access the PCI while
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* we have switched the chip select.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/mpc8xx.h>
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#include <asm/system.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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/*
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* This blows......
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* When reading the configuration space, if something does not respond
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* the bus times out and we get a machine check interrupt. So, the
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* good ol' exception tables come to mind to trap it and return some
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* value.
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*
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* On an error we just return a -1, since that is what the caller wants
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* returned if nothing is present. I copied this from __get_user_asm,
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* with the only difference of returning -1 instead of EFAULT.
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* There is an associated hack in the machine check trap code.
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*
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* The QSPAN is also a big endian device, that is it makes the PCI
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* look big endian to us. This presents a problem for the Linux PCI
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* functions, which assume little endian. For example, we see the
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* first 32-bit word like this:
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* ------------------------
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* | Device ID | Vendor ID |
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* ------------------------
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* If we read/write as a double word, that's OK. But in our world,
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* when read as a word, device ID is at location 0, not location 2 as
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* the little endian PCI would believe. We have to switch bits in
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* the PCI addresses given to us to get the data to/from the correct
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* byte lanes.
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*
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* The QSPAN only supports 4 bits of "slot" in the dev_fn instead of 5.
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* It always forces the MS bit to zero. Therefore, dev_fn values
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* greater than 128 are returned as "no device found" errors.
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*
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* The QSPAN can only perform long word (32-bit) configuration cycles.
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* The "offset" must have the two LS bits set to zero. Read operations
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* require we read the entire word and then sort out what should be
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* returned. Write operations other than long word require that we
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* read the long word, update the proper word or byte, then write the
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* entire long word back.
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*
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* PCI Bridge hack. We assume (correctly) that bus 0 is the primary
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* PCI bus from the QSPAN. If we are called with a bus number other
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* than zero, we create a Type 1 configuration access that a downstream
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* PCI bridge will interpret.
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*/
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#define __get_qspan_pci_config(x, addr, op) \
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__asm__ __volatile__( \
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"1: "op" %0,0(%1)\n" \
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" eieio\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3: li %0,-1\n" \
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" b 2b\n" \
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".section __ex_table,\"a\"\n" \
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" .align 2\n" \
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" .long 1b,3b\n" \
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".text" \
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: "=r"(x) : "r"(addr) : " %0")
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#define QS_CONFIG_ADDR ((volatile uint *)(PCI_CSR_ADDR + 0x500))
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#define QS_CONFIG_DATA ((volatile uint *)(PCI_CSR_ADDR + 0x504))
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#define mk_config_addr(bus, dev, offset) \
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(((bus)<<16) | ((dev)<<8) | (offset & 0xfc))
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#define mk_config_type1(bus, dev, offset) \
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mk_config_addr(bus, dev, offset) | 1;
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static spinlock_t pcibios_lock = SPIN_LOCK_UNLOCKED;
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int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned char *val)
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{
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uint temp;
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u_char *cp;
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#ifdef CONFIG_RPXCLASSIC
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unsigned long flags;
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#endif
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if ((bus > 7) || (dev_fn > 127)) {
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*val = 0xff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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#ifdef CONFIG_RPXCLASSIC
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/* disable interrupts */
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spin_lock_irqsave(&pcibios_lock, flags);
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*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
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eieio();
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#endif
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if (bus == 0)
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*QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
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else
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*QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
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__get_qspan_pci_config(temp, QS_CONFIG_DATA, "lwz");
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#ifdef CONFIG_RPXCLASSIC
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*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
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eieio();
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spin_unlock_irqrestore(&pcibios_lock, flags);
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#endif
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offset ^= 0x03;
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cp = ((u_char *)&temp) + (offset & 0x03);
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*val = *cp;
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return PCIBIOS_SUCCESSFUL;
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}
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int qspan_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned short *val)
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{
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uint temp;
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ushort *sp;
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#ifdef CONFIG_RPXCLASSIC
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unsigned long flags;
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#endif
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if ((bus > 7) || (dev_fn > 127)) {
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*val = 0xffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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#ifdef CONFIG_RPXCLASSIC
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/* disable interrupts */
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spin_lock_irqsave(&pcibios_lock, flags);
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*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
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eieio();
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#endif
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if (bus == 0)
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*QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
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else
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*QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
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__get_qspan_pci_config(temp, QS_CONFIG_DATA, "lwz");
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offset ^= 0x02;
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#ifdef CONFIG_RPXCLASSIC
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*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
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eieio();
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spin_unlock_irqrestore(&pcibios_lock, flags);
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#endif
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sp = ((ushort *)&temp) + ((offset >> 1) & 1);
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*val = *sp;
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return PCIBIOS_SUCCESSFUL;
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}
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int qspan_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned int *val)
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{
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#ifdef CONFIG_RPXCLASSIC
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unsigned long flags;
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#endif
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if ((bus > 7) || (dev_fn > 127)) {
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*val = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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#ifdef CONFIG_RPXCLASSIC
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/* disable interrupts */
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spin_lock_irqsave(&pcibios_lock, flags);
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*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
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eieio();
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#endif
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if (bus == 0)
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*QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
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else
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*QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
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__get_qspan_pci_config(*val, QS_CONFIG_DATA, "lwz");
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#ifdef CONFIG_RPXCLASSIC
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*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
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eieio();
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spin_unlock_irqrestore(&pcibios_lock, flags);
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#endif
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return PCIBIOS_SUCCESSFUL;
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}
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int qspan_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned char val)
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{
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uint temp;
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u_char *cp;
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#ifdef CONFIG_RPXCLASSIC
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unsigned long flags;
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#endif
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if ((bus > 7) || (dev_fn > 127))
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return PCIBIOS_DEVICE_NOT_FOUND;
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qspan_pcibios_read_config_dword(bus, dev_fn, offset, &temp);
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offset ^= 0x03;
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cp = ((u_char *)&temp) + (offset & 0x03);
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*cp = val;
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#ifdef CONFIG_RPXCLASSIC
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/* disable interrupts */
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spin_lock_irqsave(&pcibios_lock, flags);
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*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
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eieio();
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#endif
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if (bus == 0)
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*QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
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else
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*QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
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*QS_CONFIG_DATA = temp;
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#ifdef CONFIG_RPXCLASSIC
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*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
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eieio();
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spin_unlock_irqrestore(&pcibios_lock, flags);
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#endif
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return PCIBIOS_SUCCESSFUL;
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}
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int qspan_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned short val)
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{
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uint temp;
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ushort *sp;
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#ifdef CONFIG_RPXCLASSIC
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unsigned long flags;
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#endif
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if ((bus > 7) || (dev_fn > 127))
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return PCIBIOS_DEVICE_NOT_FOUND;
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qspan_pcibios_read_config_dword(bus, dev_fn, offset, &temp);
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offset ^= 0x02;
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sp = ((ushort *)&temp) + ((offset >> 1) & 1);
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*sp = val;
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#ifdef CONFIG_RPXCLASSIC
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/* disable interrupts */
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spin_lock_irqsave(&pcibios_lock, flags);
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*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
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eieio();
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#endif
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if (bus == 0)
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*QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
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else
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*QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
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*QS_CONFIG_DATA = temp;
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#ifdef CONFIG_RPXCLASSIC
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*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
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eieio();
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spin_unlock_irqrestore(&pcibios_lock, flags);
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#endif
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return PCIBIOS_SUCCESSFUL;
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}
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int qspan_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned int val)
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{
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#ifdef CONFIG_RPXCLASSIC
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unsigned long flags;
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#endif
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if ((bus > 7) || (dev_fn > 127))
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return PCIBIOS_DEVICE_NOT_FOUND;
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#ifdef CONFIG_RPXCLASSIC
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/* disable interrupts */
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spin_lock_irqsave(&pcibios_lock, flags);
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*((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
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eieio();
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#endif
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if (bus == 0)
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*QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
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else
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*QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
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*(unsigned int *)QS_CONFIG_DATA = val;
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#ifdef CONFIG_RPXCLASSIC
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*((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
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eieio();
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spin_unlock_irqrestore(&pcibios_lock, flags);
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#endif
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return PCIBIOS_SUCCESSFUL;
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}
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int qspan_pcibios_find_device(unsigned short vendor, unsigned short dev_id,
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unsigned short index, unsigned char *bus_ptr,
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unsigned char *dev_fn_ptr)
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{
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int num, devfn;
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unsigned int x, vendev;
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if (vendor == 0xffff)
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return PCIBIOS_BAD_VENDOR_ID;
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vendev = (dev_id << 16) + vendor;
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num = 0;
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for (devfn = 0; devfn < 32; devfn++) {
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qspan_pcibios_read_config_dword(0, devfn<<3, PCI_VENDOR_ID, &x);
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if (x == vendev) {
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if (index == num) {
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*bus_ptr = 0;
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*dev_fn_ptr = devfn<<3;
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return PCIBIOS_SUCCESSFUL;
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}
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++num;
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}
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}
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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int qspan_pcibios_find_class(unsigned int class_code, unsigned short index,
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unsigned char *bus_ptr, unsigned char *dev_fn_ptr)
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{
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int devnr, x, num;
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num = 0;
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for (devnr = 0; devnr < 32; devnr++) {
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qspan_pcibios_read_config_dword(0, devnr<<3, PCI_CLASS_REVISION, &x);
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if ((x>>8) == class_code) {
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if (index == num) {
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*bus_ptr = 0;
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*dev_fn_ptr = devnr<<3;
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return PCIBIOS_SUCCESSFUL;
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}
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++num;
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}
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}
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|
return PCIBIOS_DEVICE_NOT_FOUND;
|
||
|
|
}
|
||
|
|
|
||
|
|
void __init
|
||
|
|
m8xx_pcibios_fixup(void))
|
||
|
|
{
|
||
|
|
/* Lots to do here, all board and configuration specific. */
|
||
|
|
}
|
||
|
|
|
||
|
|
void __init
|
||
|
|
m8xx_setup_pci_ptrs(void))
|
||
|
|
{
|
||
|
|
set_config_access_method(qspan);
|
||
|
|
|
||
|
|
ppc_md.pcibios_fixup = m8xx_pcibios_fixup;
|
||
|
|
}
|
||
|
|
|