457 lines
8.8 KiB
ArmAsm
457 lines
8.8 KiB
ArmAsm
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/*
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* File: arch/blackfin/mach-bf527/head.S
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* Based on: arch/blackfin/mach-bf533/head.S
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* Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
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*
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* Created: 1998
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* Description: Startup code for Blackfin BF537
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*
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* Modified:
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/blackfin.h>
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#include <asm/trace.h>
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#if CONFIG_BFIN_KERNEL_CLOCK
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#include <asm/mach-common/clocks.h>
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#include <asm/mach/mem_init.h>
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#endif
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.global __rambase
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.global __ramstart
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.global __ramend
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.extern ___bss_stop
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.extern ___bss_start
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.extern _bf53x_relocate_l1_mem
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#define INITIAL_STACK 0xFFB01000
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__INIT
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ENTRY(__start)
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/* R0: argument of command line string, passed from uboot, save it */
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R7 = R0;
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/* Enable Cycle Counter and Nesting Of Interrupts */
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#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
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R0 = SYSCFG_SNEN;
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#else
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R0 = SYSCFG_SNEN | SYSCFG_CCEN;
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#endif
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SYSCFG = R0;
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R0 = 0;
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/* Clear Out All the data and pointer Registers */
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R1 = R0;
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R2 = R0;
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R3 = R0;
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R4 = R0;
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R5 = R0;
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R6 = R0;
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P0 = R0;
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P1 = R0;
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P2 = R0;
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P3 = R0;
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P4 = R0;
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P5 = R0;
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LC0 = r0;
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LC1 = r0;
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L0 = r0;
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L1 = r0;
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L2 = r0;
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L3 = r0;
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/* Clear Out All the DAG Registers */
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B0 = r0;
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B1 = r0;
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B2 = r0;
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B3 = r0;
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I0 = r0;
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I1 = r0;
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I2 = r0;
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I3 = r0;
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M0 = r0;
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M1 = r0;
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M2 = r0;
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M3 = r0;
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trace_buffer_init(p0,r0);
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P0 = R1;
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R0 = R1;
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/* Turn off the icache */
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p0.l = LO(IMEM_CONTROL);
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p0.h = HI(IMEM_CONTROL);
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R1 = [p0];
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R0 = ~ENICPLB;
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R0 = R0 & R1;
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/* Anomaly 05000125 */
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#if ANOMALY_05000125
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CLI R2;
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SSYNC;
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#endif
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[p0] = R0;
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SSYNC;
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#if ANOMALY_05000125
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STI R2;
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#endif
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/* Turn off the dcache */
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p0.l = LO(DMEM_CONTROL);
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p0.h = HI(DMEM_CONTROL);
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R1 = [p0];
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R0 = ~ENDCPLB;
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R0 = R0 & R1;
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/* Anomaly 05000125 */
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#if ANOMALY_05000125
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CLI R2;
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SSYNC;
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#endif
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[p0] = R0;
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SSYNC;
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#if ANOMALY_05000125
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STI R2;
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#endif
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#if defined(CONFIG_BF527)
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p0.h = hi(EMAC_SYSTAT);
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p0.l = lo(EMAC_SYSTAT);
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R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
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R0.l = 0xFFFF;
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[P0] = R0;
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SSYNC;
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#endif
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/* Initialise UART - when booting from u-boot, the UART is not disabled
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* so if we dont initalize here, our serial console gets hosed */
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p0.h = hi(UART1_LCR);
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p0.l = lo(UART1_LCR);
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r0 = 0x0(Z);
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w[p0] = r0.L; /* To enable DLL writes */
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ssync;
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p0.h = hi(UART1_DLL);
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p0.l = lo(UART1_DLL);
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r0 = 0x0(Z);
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w[p0] = r0.L;
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ssync;
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p0.h = hi(UART1_DLH);
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p0.l = lo(UART1_DLH);
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r0 = 0x00(Z);
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w[p0] = r0.L;
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ssync;
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p0.h = hi(UART1_GCTL);
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p0.l = lo(UART1_GCTL);
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r0 = 0x0(Z);
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w[p0] = r0.L; /* To enable UART clock */
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ssync;
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/* Initialize stack pointer */
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sp.l = lo(INITIAL_STACK);
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sp.h = hi(INITIAL_STACK);
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fp = sp;
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usp = sp;
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#ifdef CONFIG_EARLY_PRINTK
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SP += -12;
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call _init_early_exception_vectors;
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SP += 12;
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#endif
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/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
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call _bf53x_relocate_l1_mem;
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#if CONFIG_BFIN_KERNEL_CLOCK
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call _start_dma_code;
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#endif
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/* Code for initializing Async memory banks */
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p2.h = hi(EBIU_AMBCTL1);
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p2.l = lo(EBIU_AMBCTL1);
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r0.h = hi(AMBCTL1VAL);
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r0.l = lo(AMBCTL1VAL);
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[p2] = r0;
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ssync;
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p2.h = hi(EBIU_AMBCTL0);
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p2.l = lo(EBIU_AMBCTL0);
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r0.h = hi(AMBCTL0VAL);
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r0.l = lo(AMBCTL0VAL);
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[p2] = r0;
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ssync;
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p2.h = hi(EBIU_AMGCTL);
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p2.l = lo(EBIU_AMGCTL);
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r0 = AMGCTLVAL;
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w[p2] = r0;
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ssync;
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/* This section keeps the processor in supervisor mode
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* during kernel boot. Switches to user mode at end of boot.
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* See page 3-9 of Hardware Reference manual for documentation.
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*/
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/* EVT15 = _real_start */
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p0.l = lo(EVT15);
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p0.h = hi(EVT15);
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p1.l = _real_start;
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p1.h = _real_start;
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[p0] = p1;
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csync;
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p0.l = lo(IMASK);
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p0.h = hi(IMASK);
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p1.l = IMASK_IVG15;
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p1.h = 0x0;
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[p0] = p1;
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csync;
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raise 15;
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p0.l = .LWAIT_HERE;
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p0.h = .LWAIT_HERE;
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reti = p0;
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#if ANOMALY_05000281
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nop; nop; nop;
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#endif
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rti;
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.LWAIT_HERE:
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jump .LWAIT_HERE;
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ENDPROC(__start)
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ENTRY(_real_start)
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[ -- sp ] = reti;
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p0.l = lo(WDOG_CTL);
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p0.h = hi(WDOG_CTL);
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r0 = 0xAD6(z);
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w[p0] = r0; /* watchdog off for now */
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ssync;
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/* Code update for BSS size == 0
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* Zero out the bss region.
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*/
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p1.l = ___bss_start;
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p1.h = ___bss_start;
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p2.l = ___bss_stop;
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p2.h = ___bss_stop;
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r0 = 0;
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p2 -= p1;
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lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
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.L_clear_bss:
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B[p1++] = r0;
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/* In case there is a NULL pointer reference
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* Zero out region before stext
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*/
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p1.l = 0x0;
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p1.h = 0x0;
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r0.l = __stext;
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r0.h = __stext;
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r0 = r0 >> 1;
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p2 = r0;
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r0 = 0;
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lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
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.L_clear_zero:
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W[p1++] = r0;
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/* pass the uboot arguments to the global value command line */
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R0 = R7;
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call _cmdline_init;
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p1.l = __rambase;
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p1.h = __rambase;
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r0.l = __sdata;
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r0.h = __sdata;
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[p1] = r0;
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p1.l = __ramstart;
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p1.h = __ramstart;
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p3.l = ___bss_stop;
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p3.h = ___bss_stop;
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r1 = p3;
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[p1] = r1;
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/*
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* load the current thread pointer and stack
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*/
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r1.l = _init_thread_union;
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r1.h = _init_thread_union;
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r2.l = 0x2000;
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r2.h = 0x0000;
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r1 = r1 + r2;
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sp = r1;
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usp = sp;
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fp = sp;
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jump.l _start_kernel;
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ENDPROC(_real_start)
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__FINIT
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.section .l1.text
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#if CONFIG_BFIN_KERNEL_CLOCK
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ENTRY(_start_dma_code)
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/* Enable PHY CLK buffer output */
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p0.h = hi(VR_CTL);
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p0.l = lo(VR_CTL);
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r0.l = w[p0];
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bitset(r0, 14);
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w[p0] = r0.l;
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ssync;
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p0.h = hi(SIC_IWR0);
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p0.l = lo(SIC_IWR0);
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r0.l = 0x1;
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r0.h = 0x0;
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[p0] = r0;
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SSYNC;
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/*
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* Set PLL_CTL
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* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
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* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
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* - [7] = output delay (add 200ps of delay to mem signals)
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* - [6] = input delay (add 200ps of input delay to mem signals)
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* - [5] = PDWN : 1=All Clocks off
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* - [3] = STOPCK : 1=Core Clock off
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* - [1] = PLL_OFF : 1=Disable Power to PLL
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* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
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* all other bits set to zero
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*/
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p0.h = hi(PLL_LOCKCNT);
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p0.l = lo(PLL_LOCKCNT);
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r0 = 0x300(Z);
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w[p0] = r0.l;
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ssync;
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P2.H = hi(EBIU_SDGCTL);
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P2.L = lo(EBIU_SDGCTL);
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R0 = [P2];
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BITSET (R0, 24);
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[P2] = R0;
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SSYNC;
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r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
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r0 = r0 << 9; /* Shift it over, */
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r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
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r0 = r1 | r0;
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r1 = PLL_BYPASS; /* Bypass the PLL? */
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r1 = r1 << 8; /* Shift it over */
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r0 = r1 | r0; /* add them all together */
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p0.h = hi(PLL_CTL);
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p0.l = lo(PLL_CTL); /* Load the address */
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cli r2; /* Disable interrupts */
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ssync;
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w[p0] = r0.l; /* Set the value */
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idle; /* Wait for the PLL to stablize */
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|
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sti r2; /* Enable interrupts */
|
||
|
|
|
||
|
|
.Lcheck_again:
|
||
|
|
p0.h = hi(PLL_STAT);
|
||
|
|
p0.l = lo(PLL_STAT);
|
||
|
|
R0 = W[P0](Z);
|
||
|
|
CC = BITTST(R0,5);
|
||
|
|
if ! CC jump .Lcheck_again;
|
||
|
|
|
||
|
|
/* Configure SCLK & CCLK Dividers */
|
||
|
|
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
|
||
|
|
p0.h = hi(PLL_DIV);
|
||
|
|
p0.l = lo(PLL_DIV);
|
||
|
|
w[p0] = r0.l;
|
||
|
|
ssync;
|
||
|
|
|
||
|
|
p0.l = lo(EBIU_SDRRC);
|
||
|
|
p0.h = hi(EBIU_SDRRC);
|
||
|
|
r0 = mem_SDRRC;
|
||
|
|
w[p0] = r0.l;
|
||
|
|
ssync;
|
||
|
|
|
||
|
|
p0.l = LO(EBIU_SDBCTL);
|
||
|
|
p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
|
||
|
|
r0 = mem_SDBCTL;
|
||
|
|
w[p0] = r0.l;
|
||
|
|
ssync;
|
||
|
|
|
||
|
|
P2.H = hi(EBIU_SDGCTL);
|
||
|
|
P2.L = lo(EBIU_SDGCTL);
|
||
|
|
R0 = [P2];
|
||
|
|
BITCLR (R0, 24);
|
||
|
|
p0.h = hi(EBIU_SDSTAT);
|
||
|
|
p0.l = lo(EBIU_SDSTAT);
|
||
|
|
r2.l = w[p0];
|
||
|
|
cc = bittst(r2,3);
|
||
|
|
if !cc jump .Lskip;
|
||
|
|
NOP;
|
||
|
|
BITSET (R0, 23);
|
||
|
|
.Lskip:
|
||
|
|
[P2] = R0;
|
||
|
|
SSYNC;
|
||
|
|
|
||
|
|
R0.L = lo(mem_SDGCTL);
|
||
|
|
R0.H = hi(mem_SDGCTL);
|
||
|
|
R1 = [p2];
|
||
|
|
R1 = R1 | R0;
|
||
|
|
[P2] = R1;
|
||
|
|
SSYNC;
|
||
|
|
|
||
|
|
p0.h = hi(SIC_IWR0);
|
||
|
|
p0.l = lo(SIC_IWR0);
|
||
|
|
r0.l = lo(IWR_ENABLE_ALL);
|
||
|
|
r0.h = hi(IWR_ENABLE_ALL);
|
||
|
|
[p0] = r0;
|
||
|
|
SSYNC;
|
||
|
|
|
||
|
|
RTS;
|
||
|
|
ENDPROC(_start_dma_code)
|
||
|
|
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
|
||
|
|
|
||
|
|
.data
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set up the usable of RAM stuff. Size of RAM is determined then
|
||
|
|
* an initial stack set up at the end.
|
||
|
|
*/
|
||
|
|
|
||
|
|
.align 4
|
||
|
|
__rambase:
|
||
|
|
.long 0
|
||
|
|
__ramstart:
|
||
|
|
.long 0
|
||
|
|
__ramend:
|
||
|
|
.long 0
|