166 lines
4.5 KiB
C
166 lines
4.5 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef __SAMSUNG_DRM_H__
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#define __SAMSUNG_DRM_H__
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#ifdef __linux__
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#include <linux/types.h>
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#endif
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#include "drm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DRM_SAMSUNG_HDR_EOTF_LUT_LEN 129
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struct hdr_eotf_lut {
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__u16 posx[DRM_SAMSUNG_HDR_EOTF_LUT_LEN];
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__u32 posy[DRM_SAMSUNG_HDR_EOTF_LUT_LEN];
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};
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#define DRM_SAMSUNG_HDR_OETF_LUT_LEN 33
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struct hdr_oetf_lut {
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__u16 posx[DRM_SAMSUNG_HDR_OETF_LUT_LEN];
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__u16 posy[DRM_SAMSUNG_HDR_OETF_LUT_LEN];
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};
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#define DRM_SAMSUNG_HDR_GM_DIMENS 3
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struct hdr_gm_data {
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__u32 coeffs[DRM_SAMSUNG_HDR_GM_DIMENS * DRM_SAMSUNG_HDR_GM_DIMENS];
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__u32 offsets[DRM_SAMSUNG_HDR_GM_DIMENS];
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};
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#define DRM_SAMSUNG_HDR_TM_LUT_LEN 33
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struct hdr_tm_data {
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__u16 coeff_r;
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__u16 coeff_g;
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__u16 coeff_b;
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__u16 rng_x_min;
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__u16 rng_x_max;
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__u16 rng_y_min;
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__u16 rng_y_max;
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__u16 posx[DRM_SAMSUNG_HDR_TM_LUT_LEN];
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__u32 posy[DRM_SAMSUNG_HDR_TM_LUT_LEN];
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};
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#define DRM_SAMSUNG_CGC_LUT_REG_CNT 2457
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struct cgc_lut {
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__u32 r_values[DRM_SAMSUNG_CGC_LUT_REG_CNT];
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__u32 g_values[DRM_SAMSUNG_CGC_LUT_REG_CNT];
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__u32 b_values[DRM_SAMSUNG_CGC_LUT_REG_CNT];
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};
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#define DRM_SAMSUNG_CGC_DMA_LUT_ENTRY_CNT 4913
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struct cgc_dma_lut {
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__u16 r_value;
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__u16 g_value;
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__u16 b_value;
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};
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#define DRM_SAMSUNG_MATRIX_DIMENS 3
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struct exynos_matrix {
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__u16 coeffs[DRM_SAMSUNG_MATRIX_DIMENS * DRM_SAMSUNG_MATRIX_DIMENS];
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__u16 offsets[DRM_SAMSUNG_MATRIX_DIMENS];
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};
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struct dpp_size_range {
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__u32 min;
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__u32 max;
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__u32 align;
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};
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struct dpp_restriction {
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struct dpp_size_range src_f_w;
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struct dpp_size_range src_f_h;
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struct dpp_size_range src_w;
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struct dpp_size_range src_h;
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__u32 src_x_align;
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__u32 src_y_align;
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struct dpp_size_range dst_f_w;
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struct dpp_size_range dst_f_h;
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struct dpp_size_range dst_w;
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struct dpp_size_range dst_h;
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__u32 dst_x_align;
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__u32 dst_y_align;
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struct dpp_size_range blk_w;
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struct dpp_size_range blk_h;
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__u32 blk_x_align;
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__u32 blk_y_align;
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__u32 src_h_rot_max;
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__u32 scale_down;
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__u32 scale_up;
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};
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struct dpp_ch_restriction {
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__s32 id;
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__u64 attr;
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struct dpp_restriction restriction;
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};
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struct dither_config {
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__u8 en : 1;
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__u8 mode : 1;
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__u8 frame_con : 1;
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__u8 frame_offset : 2;
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__u8 table_sel_r : 1;
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__u8 table_sel_g : 1;
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__u8 table_sel_b : 1;
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__u32 reserved : 24;
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};
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struct attribute_range {
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__u32 min;
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__u32 max;
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};
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struct brightness_attribute {
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struct attribute_range nits;
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struct attribute_range level;
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struct attribute_range percentage;
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};
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struct brightness_capability {
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struct brightness_attribute normal;
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struct brightness_attribute hbm;
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};
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struct tui_hw_buffer {
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__u64 fb_physical;
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__u64 fb_size;
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} __attribute__((packed));
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#define EXYNOS_START_TUI 0x10
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#define EXYNOS_FINISH_TUI 0x11
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#define EXYNOS_TUI_REQUEST_BUFFER 0x20
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#define EXYNOS_TUI_RELEASE_BUFFER 0x21
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struct histogram_roi {
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__u16 start_x;
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__u16 start_y;
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__u16 hsize;
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__u16 vsize;
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};
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struct histogram_weights {
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__u16 weight_r;
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__u16 weight_g;
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__u16 weight_b;
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};
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#define HISTOGRAM_BIN_COUNT 256
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struct histogram_bins {
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__u16 data[HISTOGRAM_BIN_COUNT];
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};
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#define EXYNOS_DRM_HISTOGRAM_EVENT 0x80000000
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struct exynos_drm_histogram_event {
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struct drm_event base;
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struct histogram_bins bins;
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__u32 crtc_id;
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};
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enum exynos_prog_pos {
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POST_DQE,
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PRE_DQE,
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};
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#define EXYNOS_HISTOGRAM_REQUEST 0x0
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#define EXYNOS_HISTOGRAM_CANCEL 0x1
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#define DRM_IOCTL_EXYNOS_HISTOGRAM_REQUEST DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_REQUEST, __u32)
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#define DRM_IOCTL_EXYNOS_HISTOGRAM_CANCEL DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_CANCEL, __u32)
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#ifdef __cplusplus
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}
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#endif
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#endif
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